公开(公告)号：US11874778B2

公开(公告)日：2024-01-16

申请号：US16625943

申请日：2018-06-11

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Matthew Lucien Evans ,  Gareth Rhys Stockwell ,  Djordje Kovacevic

IPC: G06F12/14 ,  G06F12/02 ,  G06F21/62

CPC classification number: G06F12/1458 ,  G06F12/0253 ,  G06F21/6218 ,  G06F2212/1044

Abstract: Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry. A realm management unit (RMU) is provided to perform realm management operations for managing the realms. The memory access circuitry controls access to a given memory region in dependence on at least one status attribute specifying whether the given memory region is an RMU-private memory region reserved for exclusive access by the RMU.

公开(公告)号：US11194485B2

公开(公告)日：2021-12-07

申请号：US16624039

申请日：2018-06-08

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Matthew Lucien Evans ,  Gareth Rhys Stockwell ,  Djordje Kovacevic

IPC: G06F3/06 ,  G06F12/0804

Abstract: Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry 8. In response to a realm switch from a source realm to a target realm at a more privileged exception level, state masking of a subset of architectural state associated with a source realm is performed to make the state inaccessible to a target realm. In response to a flush command following the realm switch, any of the subset of architectural state data not already saved to at least one realm execution context memory region is ensured to be saved.

公开(公告)号：US11016910B2

公开(公告)日：2021-05-25

申请号：US16623999

申请日：2018-06-11

Applicant: ARM LIMITED

Inventor： Djordje Kovacevic ,  Jason Parker ,  Matthew Lucien Evans ,  Gareth Rhys Stockwell

IPC: G06F12/14 ,  G06F12/10 ,  G06Q10/10

Abstract: Apparatus for processing data uses memory access circuitry to enforce ownership rights of a plurality of memory regions within a memory, a given memory region among the plurality of memory regions having a given owning process specified from among a plurality of processes. A given owning process has exclusive rights to control access to given owned data stored within the given memory region. The memory access circuitry is responsive to a first access command from a first processing element for the given memory region to perform an access sequence comprising switching a lock flag for the given memory region to a locked state, performing an access operation specified by the access command, and switching the lock flag to an unlocked state. The memory access circuitry is responsive to a second access command from a second processing element for the given memory region while the lock flag is in said locked state to block action of the second access command.

公开(公告)号：US11816227B2

公开(公告)日：2023-11-14

申请号：US16624474

申请日：2018-06-11

Applicant: ARM LIMITED

Inventor： Gareth Rhys Stockwell ,  Jason Parker ,  Djordje Kovacevic ,  Matthew Lucien Evans

IPC: G06F21/60 ,  G06F9/455 ,  G06F9/48 ,  G06F12/14 ,  G06F21/79

CPC classification number: G06F21/602 ,  G06F9/45558 ,  G06F9/4812 ,  G06F12/1491 ,  G06F21/79 ,  G06F2009/45583 ,  G06F2009/45587 ,  G06F2212/1052

Abstract: An apparatus for processing data comprises memory access circuitry to enforce ownership rights of a plurality of memory regions within a first memory. The memory access circuitry is responsive to a first export command received from a first export command source to perform a first export operation to encrypt the given owned data to form given encrypted data and to store the given encrypted data in a second memory. The memory access circuitry is responsive to a second export command for the given memory region received from a second export command source while the first export operation is being performed to determine whether said second export command source has higher priority than the first export command source and, when the second export command source has a higher priority, to interrupt the first export operation and to perform a second export operation specified by the second export command.

公开(公告)号：US11449437B2

公开(公告)日：2022-09-20

申请号：US16624494

申请日：2018-06-08

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Matthew Lucien Evans ,  Gareth Rhys Stockwell ,  Djordje Kovacevic

IPC: G06F12/14 ,  G06F21/60 ,  G06F12/1036 ,  G06F9/455

Abstract: An apparatus has processing circuitry for performing data processing in response to software processes and memory access circuitry for enforcing ownership rights for memory regions. A given memory region is associated with an owner realm specified from a multiple realms with each realm corresponding to a portion of at least one software process. The owner realm has a right to exclude other realms from accessing data stored in the given memory region (including realms executed at a higher privilege level). The realms are managed according to a realm hierarchy in which each realm other than a root realm is a child realm initialised in response to a command triggered by its parent realm. In response to an invalidation command, a realm management unit makes the target realm and any descendant realm of the target realm inaccessible to the processing circuitry.

公开(公告)号：US11237957B2

公开(公告)日：2022-02-01

申请号：US16647659

申请日：2018-10-11

Applicant: ARM Limited

Inventor： Jason Parker ,  Djordje Kovacevic ,  Gareth Rhys Stockwell ,  Matthew Lucien Evans

IPC: G06F12/02 ,  G06F12/14

Abstract: A realm management unit (RMU) 20 manages ownership of memory regions by realms, each realm corresponding to at least a portion of a software process executed by processing circuitry. Memory access circuitry 26 enforces ownership rights for the regions, with the owner realm having a right to exclude other realms from accessing data stored within its owned region. The RMU 20 controls transitions of memory regions between region states, including an invalid state 220, a valid state 222, and a scrub-commit state 800 in which the memory region is allocated to an owner realm, inaccessible to that owner realm until a scrubbing process has been performed for the memory region to set each storage location of the region to a value uncorrelated with a previous value stored in the storage location, and prevented from being reallocated to a different owner realm.