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公开(公告)号：US11874778B2
公开(公告)日：2024-01-16
申请号：US16625943
申请日：2018-06-11
Applicant: ARM LIMITED
Inventor： Jason Parker , Matthew Lucien Evans , Gareth Rhys Stockwell , Djordje Kovacevic
CPC classification number: G06F12/1458 , G06F12/0253 , G06F21/6218 , G06F2212/1044
Abstract: Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry. A realm management unit (RMU) is provided to perform realm management operations for managing the realms. The memory access circuitry controls access to a given memory region in dependence on at least one status attribute specifying whether the given memory region is an RMU-private memory region reserved for exclusive access by the RMU.
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公开(公告)号：US11194485B2
公开(公告)日：2021-12-07
申请号：US16624039
申请日：2018-06-08
Applicant: ARM LIMITED
Inventor： Jason Parker , Matthew Lucien Evans , Gareth Rhys Stockwell , Djordje Kovacevic
IPC: G06F3/06 , G06F12/0804
Abstract: Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry 8. In response to a realm switch from a source realm to a target realm at a more privileged exception level, state masking of a subset of architectural state associated with a source realm is performed to make the state inaccessible to a target realm. In response to a flush command following the realm switch, any of the subset of architectural state data not already saved to at least one realm execution context memory region is ensured to be saved.
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公开(公告)号：US11461248B2
公开(公告)日：2022-10-04
申请号：US16648901
申请日：2018-11-09
Applicant: ARM Limited
Inventor： Jason Parker , Martin Weidmann , Gareth Rhys Stockwell , Matthew Lucien Evans
Abstract: A realm management unit (RMU) manages ownership of memory regions by realms, each realm corresponding to at least a portion of a software process executed by processing circuitry. Memory access circuitry enforces ownership rights for the regions, with the owner realm having a right to exclude other realms from accessing data stored within its owned region. The memory access circuitry permits execution, from within a current realm, of program code stored in a target memory region having an owner realm other than the current realm, when the target memory region is owned by a code realm and a code realm authorisation table 908 stored in at least one memory region owned by the current realm indicates that execution of program code from the target memory region is permitted by the current realm.
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公开(公告)号：US11347660B2
公开(公告)日：2022-05-31
申请号：US16623528
申请日：2018-06-11
Applicant: ARM LIMITED
Inventor： Jason Parker , Matthew Lucien Evans , Gareth Rhys Stockwell , Martin Weidmann
Abstract: Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry. A realm management unit initialises the realms. The realm management unit is configured to initialise realms including a full realm which corresponds to a given software process and a sub-realm corresponding to a given address range within the given software process.
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公开(公告)号：US11294676B2
公开(公告)日：2022-04-05
申请号：US16625912
申请日：2018-06-08
Applicant: ARM LIMITED
Inventor： Matthew Lucien Evans , Jason Parker , Gareth Rhys Stockwell , Martin Weidmann
Abstract: Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry. In response to a first variant of an exception return instruction the processing circuitry returns from processing of an exception while staying within the same realm. In response to a second variant of the exception return instruction the processing circuitry switches processing from a current realm to a destination realm.
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Patent Agency Ranking
公开(公告)号：US11816227B2
公开(公告)日：2023-11-14
申请号：US16624474
申请日：2018-06-11
Applicant: ARM LIMITED
Inventor： Gareth Rhys Stockwell , Jason Parker , Djordje Kovacevic , Matthew Lucien Evans
CPC classification number: G06F21/602 , G06F9/45558 , G06F9/4812 , G06F12/1491 , G06F21/79 , G06F2009/45583 , G06F2009/45587 , G06F2212/1052
Abstract: An apparatus for processing data comprises memory access circuitry to enforce ownership rights of a plurality of memory regions within a first memory. The memory access circuitry is responsive to a first export command received from a first export command source to perform a first export operation to encrypt the given owned data to form given encrypted data and to store the given encrypted data in a second memory. The memory access circuitry is responsive to a second export command for the given memory region received from a second export command source while the first export operation is being performed to determine whether said second export command source has higher priority than the first export command source and, when the second export command source has a higher priority, to interrupt the first export operation and to perform a second export operation specified by the second export command.
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公开(公告)号：US11449437B2
公开(公告)日：2022-09-20
申请号：US16624494
申请日：2018-06-08
Applicant: ARM LIMITED
Inventor： Jason Parker , Matthew Lucien Evans , Gareth Rhys Stockwell , Djordje Kovacevic
IPC: G06F12/14 , G06F21/60 , G06F12/1036 , G06F9/455
Abstract: An apparatus has processing circuitry for performing data processing in response to software processes and memory access circuitry for enforcing ownership rights for memory regions. A given memory region is associated with an owner realm specified from a multiple realms with each realm corresponding to a portion of at least one software process. The owner realm has a right to exclude other realms from accessing data stored in the given memory region (including realms executed at a higher privilege level). The realms are managed according to a realm hierarchy in which each realm other than a root realm is a child realm initialised in response to a command triggered by its parent realm. In response to an invalidation command, a realm management unit makes the target realm and any descendant realm of the target realm inaccessible to the processing circuitry.
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公开(公告)号：US11237957B2
公开(公告)日：2022-02-01
申请号：US16647659
申请日：2018-10-11
Applicant: ARM Limited
Inventor： Jason Parker , Djordje Kovacevic , Gareth Rhys Stockwell , Matthew Lucien Evans
Abstract: A realm management unit (RMU) 20 manages ownership of memory regions by realms, each realm corresponding to at least a portion of a software process executed by processing circuitry. Memory access circuitry 26 enforces ownership rights for the regions, with the owner realm having a right to exclude other realms from accessing data stored within its owned region. The RMU 20 controls transitions of memory regions between region states, including an invalid state 220, a valid state 222, and a scrub-commit state 800 in which the memory region is allocated to an owner realm, inaccessible to that owner realm until a scrubbing process has been performed for the memory region to set each storage location of the region to a value uncorrelated with a previous value stored in the storage location, and prevented from being reallocated to a different owner realm.
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公开(公告)号：US11113209B2
公开(公告)日：2021-09-07
申请号：US16625924
申请日：2018-06-08
Applicant: ARM LIMITED
Inventor： Matthew Lucien Evans , Jason Parker , Gareth Rhys Stockwell , Martin Weidmann
IPC: G06F12/14 , G06F12/08 , G06F12/0802 , G06F12/0891 , G06F12/1027
Abstract: An apparatus has a translation cache (100) comprising a number of entries for specifying address translation data. Each entry (260) also specifies a translation context identifier (254) associated with the address translation data and a realm identifier (270) identifying one of a number of realms. Each realm corresponds to at least a portion of at least one software process executed by processing circuitry (8). In response to a memory access a lookup of the translation cache (100) is triggered. When the lookup misses in the cache (100), control circuitry (280) prevents allocation of address translation data to the cache when the current realm is excluded from accessing the target memory region by an owner realm specified for the target memory region. In the lookup, whether a given entry (260) matches the memory access depends on both a translation context identifier comparison and a realm identifier comparison.
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公开(公告)号：US20240403223A1
公开(公告)日：2024-12-05
申请号：US18699127
申请日：2022-08-31
Applicant: Arm Limited
Inventor： Christoffer Dall , Mark Salling Rutland , Gareth Rhys Stockwell
IPC: G06F12/1009
Abstract: There is provided address translation circuitry and a method for performing address translation. The address translation circuitry is responsive to receipt of a first address and an identifier to perform an address translation from the first address to a second address by performing a translation table walk comprising one or more translation lookups in a plurality of translation tables that are indexed based on a corresponding portion of the first address. The address translation circuitry is further configured to perform a metadata table walk to determine metadata specific to the identifier and associated with the address translation. The metadata table walk comprises one or more metadata lookups in a plurality of metadata lookup tables, each of the one or more metadata lookups corresponds to one of the one or more translation lookups and is indexed based on a same portion of the first address as that translation.
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