公开(公告)号：US12045154B2

公开(公告)日：2024-07-23

申请号：US17998299

申请日：2021-05-13

Applicant: Arm Limited

Inventor： John Michael Horley ,  Michael John Williams ,  Mark Salling Rutland ,  Alasdair Grant

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/34 ,  G06F11/36

CPC classification number: G06F11/3466 ,  G06F9/3867 ,  G06F11/34 ,  G06F11/3636 ,  G06F9/3861 ,  G06F9/3865 ,  G06F2201/86 ,  G06F2201/865

Abstract: A technique for collecting state information of an apparatus comprising a processing pipeline for executing a sequence of instructions, and interesting instruction designation circuitry for identifying at least one of the instructions in the sequence as being an interesting instruction. Each interesting instruction is an instruction for which given state information of the apparatus associated with execution of that interesting instruction is to be collected. The interesting instruction designation circuitry is arranged, for each identified interesting instruction, to apply defined selection criteria to determine a further instruction later in the sequence of instructions than the interesting instruction, and to mark that further instruction as having a synchronous exception associated therewith. The processing pipeline is responsive to the further instruction, which causes the processing pipeline to execute a given exception handling routine in order to collect the given state information.

公开(公告)号：US20240403223A1

公开(公告)日：2024-12-05

申请号：US18699127

申请日：2022-08-31

Applicant: Arm Limited

Inventor： Christoffer Dall ,  Mark Salling Rutland ,  Gareth Rhys Stockwell

IPC: G06F12/1009

Abstract: There is provided address translation circuitry and a method for performing address translation. The address translation circuitry is responsive to receipt of a first address and an identifier to perform an address translation from the first address to a second address by performing a translation table walk comprising one or more translation lookups in a plurality of translation tables that are indexed based on a corresponding portion of the first address. The address translation circuitry is further configured to perform a metadata table walk to determine metadata specific to the identifier and associated with the address translation. The metadata table walk comprises one or more metadata lookups in a plurality of metadata lookup tables, each of the one or more metadata lookups corresponds to one of the one or more translation lookups and is indexed based on a same portion of the first address as that translation.

公开(公告)号：US11726839B2

公开(公告)日：2023-08-15

申请号：US17446796

申请日：2021-09-02

Applicant: Arm Limited

Inventor： Mark Salling Rutland ,  Gareth Rhys Stockwell ,  Christoffer Dall ,  Jade Ella Carla Alglave

IPC: G06F9/52 ,  G06F9/48

CPC classification number: G06F9/524 ,  G06F9/4881

Abstract: Apparatus comprises a data memory to store lock data for each of a set of processing resources, the lock data representing lock status data and tag data indicating a resource type selected from a plurality of resource types; and a processing element to execute an atomic operation with respect to the lock data for a given processing resource, the atomic operation comprising at least: a detection of whether the given processing resource is of a required resource type; a detection from the lock status data whether the given processing resource is currently unlocked; and when the given processing resource is detected to be currently unlocked and of the required resource type, performance of a predetermined action with respect to one or both of the lock status data and the tag data.