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公开(公告)号：US09747658B2
公开(公告)日：2017-08-29
申请号：US14019909
申请日：2013-09-06
Applicant: Apple Inc.
Inventor： Peter F. Holland , Albert C. Kuo , Hao Chen
IPC: G06T1/20
CPC classification number: G06T1/20
Abstract: Embodiments of an apparatus and method are disclosed that may allow for arbitrating multiple read requests to fetch pixel data from a memory. The apparatus may include a first and a second processing pipeline, and a control unit. Each of the processing pipelines may be configured to generate a plurality of read requests to fetch a respective one of a plurality of portions of stored pixel data. The control unit may be configured to determine a priority for each read request dependent upon display coordinates of one or more pixels corresponding to each of the plurality of portions of stored pixel data, and determine an order for the plurality of read requests dependent upon the determined priority for each read request.
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公开(公告)号：US09454378B2
公开(公告)日：2016-09-27
申请号：US14083010
申请日：2013-11-18
Applicant: Apple Inc.
Inventor： Guy Cote , Joseph P. Bratt , Nitin Bhargava , Hao Chen , Joseph J. Cheng
CPC classification number: G06F9/4401 , G06F3/0629 , G06F8/71 , G06F9/445
Abstract: Methods and apparatus for configuring multiple components of a subsystem are described. The configuration memory of each of a plurality of components coupled to an interconnect includes a global configuration portion. The configuration memory of one of the components may be designated as a master global configuration for all of the components. A module coupled to the interconnect may receive writes to the components from a configuration source. For each write, the module may decode the write to determine addressing information and check to see if the write is addressed to the master global configuration. If the write is addressed to the master global configuration, the module broadcasts the write to the global configuration portion of each of the components via the interconnect. If the write is not addressed to the master global configuration, the module forwards the write to the appropriate component via the interconnect.
Abstract translation: 描述用于配置子系统的多个组件的方法和装置。 耦合到互连的多个组件中的每一个的配置存储器包括全局配置部分。 可以将组件之一的配置存储器指定为用于所有组件的主全局配置。 耦合到互连的模块可以从配置源接收对组件的写入。 对于每次写入，模块可以解码写入以确定寻址信息，并检查写入是否寻址到主全局配置。 如果写入寻址到主全局配置，则模块通过互连广播写入每个组件的全局配置部分。 如果写入不适用于主全局配置，则模块通过互连将写入转发到相应的组件。
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公开(公告)号：US20150095630A1
公开(公告)日：2015-04-02
申请号：US14083010
申请日：2013-11-18
Applicant: Apple Inc.
Inventor： Guy Cote , Joseph P. Bratt , Nitin Bhargava , Hao Chen , Joseph J. Cheng
IPC: G06F9/44
CPC classification number: G06F9/4401 , G06F3/0629 , G06F8/71 , G06F9/445
Abstract: Methods and apparatus for configuring multiple components of a subsystem are described. The configuration memory of each of a plurality of components coupled to an interconnect includes a global configuration portion. The configuration memory of one of the components may be designated as a master global configuration for all of the components. A module coupled to the interconnect may receive writes to the components from a configuration source. For each write, the module may decode the write to determine addressing information and check to see if the write is addressed to the master global configuration. If the write is addressed to the master global configuration, the module broadcasts the write to the global configuration portion of each of the components via the interconnect. If the write is not addressed to the master global configuration, the module forwards the write to the appropriate component via the interconnect.
Abstract translation: 描述用于配置子系统的多个组件的方法和装置。 耦合到互连的多个组件中的每一个的配置存储器包括全局配置部分。 可以将组件之一的配置存储器指定为用于所有组件的主全局配置。 耦合到互连的模块可以从配置源接收对组件的写入。 对于每次写入，模块可以解码写入以确定寻址信息，并检查写入是否寻址到主全局配置。 如果写入寻址到主全局配置，则模块通过互连广播写入每个组件的全局配置部分。 如果写入不适用于主全局配置，则模块通过互连将写入转发到相应的组件。
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公开(公告)号：US20130046938A1
公开(公告)日：2013-02-21
申请号：US13653109
申请日：2012-10-16
Applicant: Apple Inc.
Inventor： Sukalpa Biswas , Hao Chen
IPC: G06F12/00
CPC classification number: G06F9/5033 , G06F13/1668
Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.
Abstract translation: 在一个实施例中，存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数调度在不同端口上接收的操作。 在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。 在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。
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公开(公告)号：US20250028364A1
公开(公告)日：2025-01-23
申请号：US18762440
申请日：2024-07-02
Applicant: Apple Inc.
Inventor： Wenyong Zhu , ByoungSuk Kim , Hao Chen , Sijun Niu , Wei Lv , Han-Chieh Chang , Zhen Zhang
Abstract: An electronic device may have a hinge that allows the device to be flexed about a bend axis. A display may span the bend axis. The device may have a stainless steel and/or carbon fiber reinforced polymer layer with slots. The slots may overlap the bend axis. The slots may have at least one property that varies in a non-linear manner as a function of position on the layer. The device may include an adhesive layer with a cutout that overlaps the slots. An interface that defines the cutout may have a plurality of recesses with varying depths. A flexible printed circuit may be attached to an edge of the display panel. The display cover layer may overlap a bonding region between the flexible printed circuit and the edge of the display panel. A UV-curable gap filler may be interposed between the flexible printed circuit and the display cover layer.
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Patent Agency Ranking
公开(公告)号：US20250020941A1
公开(公告)日：2025-01-16
申请号：US18737653
申请日：2024-06-07
Applicant: Apple Inc.
Inventor： Hao Chen , ByoungSuk Kim , Fu-Chung Huang , Juan He , Jun Qi , Ping-Yen Chou , Yi Huang , Yi-Pai Huang
Abstract: An electronic device may include a stereoscopic display that is configured to display three-dimensional content for a viewer. The stereoscopic display may include a lenticular lens film with lenticular lenses that extend across the length of the display and may be referred to as a lenticular display. The lenticular display may have convex curvature. The lenticular display may include a color filter layer with color filters and an opaque masking layer. The color filter layer may be interposed between the lenticular lens film and an array of display pixels for the display. The color filter layer may mitigate ghost image artifacts and reflections of ambient light. Microlenses may be included between the lenticular lens film and the array of display pixels to improve the efficiency of the display. The display may include a Fresnel lens layer. The lenticular lens film may include lenticular lenses having different shapes.
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公开(公告)号：US20240428502A1
公开(公告)日：2024-12-26
申请号：US18653567
申请日：2024-05-02
Applicant: Apple Inc.
Inventor： Fu-Chung Huang , ByoungSuk Kim , Felipe Bacim De Araujo E Silva , Hao Chen , Igor Kozintsev , Pavel V Dudrenov , Ping-Yen Chou , Seung Wook Kim , Sheng Zhang , Victor H Yin , Wei H Yao , Wei Xiong , Yang Li , Yi Huang , Yi-Pai Huang , Justin A Meiners
IPC: G06T15/06 , H04N13/133 , H04N13/305
Abstract: An electronic device may include a lenticular display. The lenticular display may have a lenticular lens film formed over an array of pixels. The lenticular lenses may be configured to enable stereoscopic viewing of the display such that a viewer perceives three-dimensional images. The display may render different content layers that present different classes of content. The different classes of content may have different characteristics. As an example, a first class of content may be static content whereas a second class of content may be dynamic content. The different characteristics of each class of content may be leveraged to use a hybrid approach for content processing. The hybrid content processing may take advantage of different layers needing to be updated at different frequencies and may take advantage of sparse content in some of the layers.
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公开(公告)号：US20200341533A1
公开(公告)日：2020-10-29
申请号：US16397888
申请日：2019-04-29
Applicant: Apple Inc.
Inventor： Ching Elizabeth Ho , Hao Chen , Nitin Bhargava , Syed F. Ali
IPC: G06F1/329 , G06F1/3228
Abstract: An apparatus includes a plurality of processor cores, a cache memory that includes a plurality of banks, and a power management circuit. The power management circuit is configured to maintain a power credit approach for the apparatus that includes tracking a total number of currently available power credits, and to store a plurality of threshold values. Each threshold value is associated with one or more of a plurality of throttling actions. In response to the total number of currently available power credits reaching a particular threshold value of the plurality of threshold values, the power management circuit performs the one or more throttling actions associated with the particular threshold value. The plurality of throttling actions includes selectively throttling one or more of the plurality of processor cores, and selectively throttling one or more of the plurality of banks in the cache memory.
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公开(公告)号：US20150302544A1
公开(公告)日：2015-10-22
申请号：US14258662
申请日：2014-04-22
Applicant: Apple Inc.
Inventor： Hao Chen , Benjamin K. Dodge , Peter F. Holland
IPC: G06T1/20
CPC classification number: G09G5/397 , G09G5/001 , G09G5/14 , G09G2340/0407 , G09G2340/10 , G09G2350/00 , G09G2352/00 , G09G2360/125
Abstract: Systems and methods for determining priorities of pixel fetch requests of separate requestors in a display control unit. The distance between the oldest pixel in an output buffer and the output equivalent coordinate of the oldest outstanding source pixel read request for each requestor in the display control unit is calculated. Then, a priority is assigned to each requestor based on this calculated distance. If a given requestor lags behind the other requestors based on a comparison of the distance between the oldest pixel and the output equivalent coordinate of the oldest outstanding source pixel read, then source pixel fetch requests for this given requestor are given a higher priority than source pixel fetch requests for the other requestors.
Abstract translation: 用于确定显示控制单元中单独请求者的像素提取请求的优先级的系统和方法。 计算输出缓冲器中的最旧像素与显示控制单元中每个请求者的最早未完成源像素读取请求的输出等效坐标之间的距离。 然后，基于该计算出的距离将优先级分配给每个请求者。 如果给定的请求者基于最旧的像素读取的最旧的源像素的输出等效坐标之间的距离的比较而落在其他请求者之后，则给予该给定请求者的源像素提取请求被给予比源像素更高的优先级 提取其他请求者的请求。
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公开(公告)号：US09105112B2
公开(公告)日：2015-08-11
申请号：US13773522
申请日：2013-02-21
Applicant: Apple Inc.
Inventor： Peter Holland , Hao Chen , Albert Kuo
CPC classification number: G06T1/60 , G06F1/3228 , G06F1/3265 , G06F1/3287 , G06T3/4007 , G09G5/363 , G09G5/391 , G09G5/395 , G09G5/399 , G09G2330/021 , G09G2340/0407 , G09G2340/045 , G09G2360/127 , Y02D10/153 , Y02D10/171 , Y02D50/20
Abstract: Techniques are disclosed relating to power management within an integrated circuit. In one embodiment, a display buffer receives image data through a data transfer interconnect. A data transfer interconnect is powered down based on the received image data being greater than a threshold amount of data. The display buffer transmits at least a portion of the image data to one or more outputs, and in response to the transmitting, the data transfer interconnect is powered up. In some embodiments, the display buffer includes a plurality of line buffers, each configured to store a respective image source line. In such an embodiment, a display pipe configured to render images to be displayed includes the display buffer, and the powering down is performed in response to the received image data including two or more image source lines.
Abstract translation: 公开了与集成电路内的电源管理有关的技术。 在一个实施例中，显示缓冲器通过数据传输互连接收图像数据。 基于接收到的图像数据大于阈值数据量，数据传输互连被断电。 显示缓冲器将图像数据的至少一部分发送到一个或多个输出，并且响应于发送，数据传输互连被加电。 在一些实施例中，显示缓冲器包括多个行缓冲器，每个行缓冲器被配置为存储相应的图像源线。 在这样的实施例中，被配置为使得要显示的图像的显示管道包括显示缓冲器，并且响应于包括两个或更多个图像源线的接收图像数据执行掉电。
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