公开(公告)号：US10963172B2

公开(公告)日：2021-03-30

申请号：US16059766

申请日：2018-08-09

Applicant: Apple Inc.

Inventor： Nachiappan Chidambaram Nachiappan ,  David L. Trawick ,  Yiu Chun Tse ,  Deniz Balkan ,  Hengsheng Geng ,  Shawn Munetoshi Fukami ,  Jaideep Dastidar ,  Benjamin K. Dodge ,  Vinodh R. Cuppu

IPC: G06F3/06 ,  G06F13/16 ,  H04W72/04 ,  H04W28/02 ,  H04L12/853

Abstract: A system and method for efficiently allocating data storage to agents. A computing system includes an interconnect with intermediate buffers for storing transactions and corresponding payload data during transport between sources and destinations. A data storage limit is set on an amount of data storage corresponding to outstanding transactions for each of the multiple sources based on the initial buffer assignments. A number of outstanding transactions for each of the multiple sources is limited based on a corresponding data storage limit. If the rate of allocation of a given buffer assigned to a first source exceeds a threshold, then a second source is selected with available space exceeding a threshold in an assigned buffer. If it is determined the second source is not assigned to a buffer with a rate of allocation exceeding a threshold, then buffer storage is reassigned from the second source to the first source.

公开(公告)号：US10298511B2

公开(公告)日：2019-05-21

申请号：US15246046

申请日：2016-08-24

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Christopher D. Shuler ,  Benjamin K. Dodge ,  Thejasvi M. Vijayaraj ,  Harshavardhan Kaushikkar ,  Yang Yang ,  Rong Z. Hu ,  Srinivasa R. Sridharan ,  Wolfgang H. Klingauf ,  Neeraj Parik

IPC: H04W72/12 ,  H04L12/863 ,  G06F13/16 ,  G06F9/54 ,  H04L12/865

Abstract: In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.

公开(公告)号：US20180063016A1

公开(公告)日：2018-03-01

申请号：US15246046

申请日：2016-08-24

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Christopher D. Shuler ,  Benjamin K. Dodge ,  Thejasvi M. Vijayaraj ,  Harshavardhan Kaushikkar ,  Yang Yang ,  Rong Z. Hu ,  Srinivasa R. Sridharan ,  Wolfgang H. Klingauf ,  Neeraj Parik

IPC: H04L12/863

CPC classification number: H04L47/6295 ,  G06F9/546 ,  G06F13/1642 ,  H04L47/6275

Abstract: In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.

公开(公告)号：US09524261B2

公开(公告)日：2016-12-20

申请号：US13724955

申请日：2012-12-21

Applicant: Apple Inc.

Inventor： Gurjeet S. Saund ,  Harshavardhan Kaushikkar ,  Benjamin K. Dodge

IPC: G06F13/00 ,  G06F3/00 ,  G06F13/38 ,  G06F13/28 ,  H04L12/801

CPC classification number: G06F13/385 ,  G06F13/28 ,  H04L47/10

Abstract: Systems and methods for preventing excessive buffering of transactions in a coherence point. The coherence point uses a lookahead mechanism to determine if there are enough credits from the memory controller for forwarding the outstanding transactions stored in the IRQ. If there are not enough credits, then the coherence point prevents the switch fabric from forwarding additional transactions to the coherence point. By preventing excessive buffering in the IRQ, the QoS-based ordering of transactions performed by the switch fabric is preserved.

Abstract translation: 在一致性点防止交易过度缓冲的系统和方法。 相干点使用前瞻机制来确定存储器控制器中是否有足够的信用来转发存储在IRQ中的未完成事务。 如果没有足够的积分，则相干点可以防止交换结构将附加事务转发到相干点。 通过防止IRQ中的过度缓冲，交换结构执行的事务的基于QoS的排序得以保留。

公开(公告)号：US11093425B2

公开(公告)日：2021-08-17

申请号：US16105252

申请日：2018-08-20

Applicant: Apple Inc.

Inventor： Nachiappan Chidambaram Nachiappan ,  Jaideep Dastidar ,  Yiu Chun Tse ,  Ripudaman Singh ,  Shawn Munetoshi Fukami ,  Benjamin K. Dodge ,  Vinodh R. Cuppu

IPC: G06F13/40 ,  G06F13/366

Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

公开(公告)号：US10795818B1

公开(公告)日：2020-10-06

申请号：US16418811

申请日：2019-05-21

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Per H. Hammarlund ,  Brian P. Lilly ,  Michael Bekerman ,  James Vash ,  Manu Gulati ,  Benjamin K. Dodge

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0817

Abstract: Various systems and methods for ensuring real-time snoop latency are disclosed. A system includes a processor and a cache controller. The cache controller receives, via a channel, cache snoop requests from the processor, the snoop requests including latency-sensitive and non-latency sensitive requests. Requests are not prioritized by type within the channel. The cache controller limits a number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop requests. Limiting the number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop request includes the cache controller determining that the number of received non-latency sensitive snoop requests has reached a predetermined value and responsively prioritizing latency-sensitive requests over non-latency sensitive requests.

公开(公告)号：US20170323419A1

公开(公告)日：2017-11-09

申请号：US15150172

申请日：2016-05-09

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Benjamin K. Dodge

IPC: G06T1/60 ,  G06T1/20 ,  G09G5/00 ,  G11B20/10

CPC classification number: G06T1/60 ,  G06T1/20 ,  G09G5/006 ,  G09G5/18 ,  G09G5/397 ,  G09G2330/021 ,  G09G2360/125 ,  G09G2360/18 ,  G11B20/10481 ,  H04N5/765

Abstract: Systems, apparatuses, and methods for time shifting tasks in a computing system. A system may include a display control unit configured to process pixels for display. The display control unit may include at least one or more pixel processing pipelines, a control unit, and a pixel buffer. The control unit may be configured to monitor the amount of data in the pixel buffer and set the priority of pixel fetch requests according to the amount of data in the pixel buffer. If the control unit determines that an inter frame period will occur within a given period of time, the control unit may prevent the priority of pixel fetch requests from being escalated if the amount of data in the pixel buffer falls below a threshold. The control unit may also be configured to fill the buffers of the display control unit with as much data as possible during the inter frame period.

公开(公告)号：US11748284B2

公开(公告)日：2023-09-05

申请号：US17375565

申请日：2021-07-14

Applicant: Apple Inc.

Inventor： Nachiappan Chidambaram Nachiappan ,  Jaideep Dastidar ,  Yiu Chun Tse ,  Ripudaman Singh ,  Shawn Munetoshi Fukami ,  Benjamin K. Dodge ,  Vinodh R. Cuppu

IPC: G06F13/366 ,  G06F13/40

CPC classification number: G06F13/366 ,  G06F13/4031

Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

公开(公告)号：US20210342282A1

公开(公告)日：2021-11-04

申请号：US17375565

申请日：2021-07-14

Applicant: Apple Inc.

Inventor： Nachiappan Chidambaram Nachiappan ,  Jaideep Dastidar ,  Yiu Chun Tse ,  Ripudaman Singh ,  Shawn Munetoshi Fukami ,  Benjamin K. Dodge ,  Vinodh R. Cuppu

IPC: G06F13/366 ,  G06F13/40

Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

公开(公告)号：US20200057737A1

公开(公告)日：2020-02-20

申请号：US16105252

申请日：2018-08-20

Applicant: Apple Inc.

Inventor： Nachiappan Chidambaram Nachiappan ,  Jaideep Dastidar ,  Yiu Chun Tse ,  Ripudaman Singh ,  Shawn Munetoshi Fukami ,  Benjamin K. Dodge ,  Vinodh R. Cuppu

IPC: G06F13/366 ,  G06F13/40

Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.