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公开(公告)号:US20240021573A1
公开(公告)日:2024-01-18
申请号:US18353019
申请日:2023-07-14
Inventor: Cyprian Emeka Uzoh , Pawel Mrozek
IPC: H01L23/00
CPC classification number: H01L24/80 , H01L24/08 , H01L2224/08145 , H01L2224/80896 , H01L2224/80013 , H01L2224/80031 , H01L2224/80895 , H01L2224/80011
Abstract: Reliable hybrid bonded apparatuses are provided. An example process cleans nanoparticles from at least the smooth oxide top layer of a surface to be hybrid bonded after the surface has already been activated for the hybrid bonding. Conventionally, such an operation is discouraged. However, the example cleaning processes described herein increase the electrical reliability of microelectronic devices. Extraneous metal nanoparticles can enable undesirable current and signal leakage from finely spaced traces, especially at higher voltages with ultra-fine trace pitches. In the example process, the extraneous nanoparticles may be both physically removed and/or dissolved without detriment to the activated bonding surface.
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公开(公告)号:US11837582B2
公开(公告)日:2023-12-05
申请号:US18148327
申请日:2022-12-29
Inventor: Guilian Gao , Cyprian Emeka Uzoh , Jeremy Alfred Theil , Belgacem Haba , Rajesh Katkar
IPC: H01L25/065 , H01L21/768 , H01L23/538 , H01L23/00
CPC classification number: H01L25/0657 , H01L21/76898 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L24/95
Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.
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公开(公告)号:US11735523B2
公开(公告)日:2023-08-22
申请号:US17314555
申请日:2021-05-07
Inventor: Cyprian Emeka Uzoh
IPC: H01L21/00 , H01L23/528 , H01L21/768
CPC classification number: H01L23/528 , H01L21/76898
Abstract: Techniques are employed to mitigate the anchoring effects of cavity sidewall adhesion on an embedded conductive interconnect structure, and to allow a lower annealing temperature to be used to join opposing conductive interconnect structures. A vertical gap may be disposed between the conductive material of an embedded interconnect structure and the sidewall of the cavity to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material. Additionally or alternatively, one or more vertical gaps may be disposed within the bonding layer, near the embedded interconnect structure to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material.
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公开(公告)号:US20230207514A1
公开(公告)日:2023-06-29
申请号:US18069783
申请日:2022-12-21
Inventor: Guilian Gao , Gaius Gillman Fountain, JR. , Cyprian Emeka Uzoh , Thomas Workman
IPC: H01L23/00 , H01L21/67 , H01L21/683
CPC classification number: H01L24/80 , H01L21/67144 , H01L21/6838 , H01L21/6831 , H01L24/74 , H01L2224/80895 , H01L2224/80896 , H01L2224/74
Abstract: A system for direct bonding can include a substrate support configured to hold a substrate for direct bonding and a die handling tool including an end effector configured to hold a die and bring the die into contact with the substrate supported on the substrate support, the end effector configured to initiate contact between the substrate and a bond initiation region of the die and to subsequently allow contact between the substrate and other regions of the die.
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公开(公告)号:US11658173B2
公开(公告)日:2023-05-23
申请号:US17131329
申请日:2020-12-22
Inventor: Cyprian Emeka Uzoh , Arkalgud R. Sitaram , Paul Enquist
IPC: H01L25/00 , H01L23/31 , H01L21/56 , H01L21/304 , H01L21/306 , H01L21/308 , H01L21/683 , H01L25/065
CPC classification number: H01L25/50 , H01L21/304 , H01L21/306 , H01L21/3081 , H01L21/561 , H01L21/683 , H01L23/3121 , H01L23/3135 , H01L25/0657 , H01L2225/06513 , H01L2225/06541 , H01L2924/1304 , H01L2924/1434 , H01L2924/1461 , H01L2924/351 , H01L2924/3511 , H01L2924/3511 , H01L2924/00 , H01L2924/1434 , H01L2924/00012 , H01L2924/1461 , H01L2924/00012 , H01L2924/1304 , H01L2924/00012
Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.
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公开(公告)号:US20230130580A1
公开(公告)日:2023-04-27
申请号:US18145282
申请日:2022-12-22
Inventor: Cyprian Emeka Uzoh , Arkalgud R. Sitaram , Paul Enquist
IPC: H01L25/00 , H01L23/31 , H01L21/56 , H01L21/304 , H01L21/306 , H01L21/308 , H01L21/683 , H01L25/065
Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.
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公开(公告)号:US20230115122A1
公开(公告)日:2023-04-13
申请号:US17931826
申请日:2022-09-13
Inventor: Cyprian Emeka Uzoh , Thomas Workman , Gabriel Z. Guevara , Dominik Suwito , Guilian Gao
IPC: H01L21/762 , H01L21/786 , H01L21/321 , H01L21/02
Abstract: Methods of bonding thin dies to substrates. In one such method, a wafer is attached to a support layer. The wafer and support layer are attached to a dicing structure and then singulated to form a plurality of semiconductor die components. Each semiconductor die component comprises a thinned die and a support layer section attached to the thinned die where each support layer section is disposed between the corresponding thinned die and the dicing structure. At least one of the semiconductor die components is then bonded to a substrate without an intervening adhesive such that the thinned die is disposed between the substrate and the support layer section. The support layer section is then removed from the thinned die.
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公开(公告)号:US12211809B2
公开(公告)日:2025-01-28
申请号:US17564550
申请日:2021-12-29
Inventor: Cyprian Emeka Uzoh
IPC: H01L23/00
Abstract: An element is disclosed. The element can include a non-conductive structure having a non-conductive bonding surface, a cavity at least partially extending through a portion of a thickness of the non-conductive structure from the non-conductive bonding surface, and a conductive pad disposed in the cavity. The cavity has a bottom side and a sidewall. The conductive pad has a bonding surface and a back side opposite the bonding surface. An average size of the grains at the bonding surface is smaller than an average size of the grains adjacent the bottom side of the cavity. The conductive pad can include a crystal structure with grains oriented along a 111 crystal plane. The element can be bonded to another element to form a bonded structure. The element and the other element can be directly bonded to one another without an intervening adhesive.
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公开(公告)号:US12198981B2
公开(公告)日:2025-01-14
申请号:US18297829
申请日:2023-04-10
Inventor: Rajesh Katkar , Cyprian Emeka Uzoh
IPC: H01L21/768 , H01L21/68 , H01L23/00 , H01L23/532 , H01L25/00 , H01L25/065
Abstract: Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.
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公开(公告)号:US12154880B2
公开(公告)日:2024-11-26
申请号:US17570880
申请日:2022-01-07
Inventor: Cyprian Emeka Uzoh
IPC: H01L23/00 , H01L25/00 , H01L25/065
Abstract: Dies and/or wafers including conductive features at the bonding surfaces are stacked and direct hybrid bonded at a reduced temperature. The surface mobility and diffusion rates of the materials of the conductive features are manipulated by adjusting one or more of the metallographic texture or orientation at the surface of the conductive features and the concentration of impurities within the materials.
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