公开(公告)号：US5525823A

公开(公告)日：1996-06-11

申请号：US242257

申请日：1994-05-13

申请人： Tsiu C. Chan

发明人： Tsiu C. Chan

IPC分类号： H01L21/8238 ,  H01L29/76 ,  H01L21/04

CPC分类号： H01L21/823878

摘要： A method for forming field oxide regions on an integrated circuit device includes the steps of providing doped regions for formation of active devices. After the doped regions have been formed, a thick field oxide layer is grown over the entire surface of the device. Field oxide regions are then defined using masking and anisotropic etching steps which provide approximately vertical sidewalls for the field oxide regions, and which do not result in the formation of bird's beaks. Since the active regions are defined prior to formation of the field oxide regions, the active regions extend under the field oxide regions and do not give rise to edge effects.

摘要翻译： 在集成电路器件上形成场氧化物区域的方法包括提供用于形成有源器件的掺杂区域的步骤。 在已经形成掺杂区域之后，在器件的整个表面上生长厚的氧化物层。 然后使用为场氧化物区域提供大致垂直侧壁的掩蔽和各向异性蚀刻步骤限定场氧化物区域，并且不会导致鸟喙的形成。 由于在形成场氧化物区域之前限定有源区域，所以有源区域在场氧化物区域的下方延伸，并且不会产生边缘效应。

公开(公告)号：US5500557A

公开(公告)日：1996-03-19

申请号：US126673

申请日：1993-09-24

申请人： Tsiu C. Chan ,  Frank R. Bryant ,  Lun-Tseng Lu ,  Che-Chia Wei

发明人： Tsiu C. Chan ,  Frank R. Bryant ,  Lun-Tseng Lu ,  Che-Chia Wei

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L23/5283 ,  H01L23/53271 ,  H01L2924/0002

摘要： A structure and method for fabricating integrated circuits which provides for the detection of residual conductive material. A first conductive layer is deposited over the integrated circuit and patterned to define a first interconnect layer. An insulating layer is then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during patterning of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.

摘要翻译： 用于制造集成电路的结构和方法，其提供残留导电材料的检测。 第一导电层沉积在集成电路上并被图案化以限定第一互连层。 然后在集成电路上形成绝缘层。 然后沉积和图案化第二导电层以限定第二互连层。 当第二导电层的部分保持与第一互连层的垂直侧壁相邻时，可以在图案化第二互连层期间形成剩余的导电材料。 为了使残留的导电材料更易于检测，通过将杂质注入集成电路或用难熔金属硅化残留的导电材料来增加剩余导电材料的导电性。

公开(公告)号：US5478771A

公开(公告)日：1995-12-26

申请号：US359006

申请日：1994-12-19

申请人： Tsiu C. Chan ,  Frank R. Bryant ,  John L. Walters

发明人： Tsiu C. Chan ,  Frank R. Bryant ,  John L. Walters

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L27/11 ,  H01L21/70

CPC分类号： H01L23/53271 ,  H01L21/76889 ,  H01L21/76895 ,  H01L27/1104 ,  H01L2924/0002 ,  Y10S148/039 ,  Y10S257/903

摘要： An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.

摘要翻译： 互连结构及其形成方法适用于诸如SRAM器件的集成电路。 该结构使用多晶硅互连电平的掩模将P-N结移动到多晶硅互连线内的区域，而不是在衬底处。 然后可以使用形成在多晶硅互连结构上的难熔金属硅化物来短路该P-N结。

公开(公告)号：US5231043A

公开(公告)日：1993-07-27

申请号：US748085

申请日：1991-08-21

申请人： Tsiu C. Chan ,  Frank R. Bryant

发明人： Tsiu C. Chan ,  Frank R. Bryant

IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L21/76802 ,  H01L27/10805

摘要： A technique for producing self-aligned contact openings is especially useful when the openings are to be made between conductive structures having relatively small separation. Formation of an oxide layer under particular process conditions results in a thicker layer of oxide on top of the conductive structures, and a thinner oxide layer along the sidewalls and in the bottom of the spacing between them. Deposition of such a differential thickness oxide layer can be followed by an unmasked-anisotropic etch in order to clear the oxide from the space between the conductive structures, without removing all of the oxide layer over the conductive structure. Such a technique can be utilized in integrated circuits such as DRAMs, with the word lines allowing for the formation of semi-self-aligned bit lines. The combination of word lines and bit lines can provide for a fully self-aligned contact opening for DRAM cell capacitors.

公开(公告)号：US5204279A

公开(公告)日：1993-04-20

申请号：US709354

申请日：1991-06-03

申请人： Tsiu C. Chan ,  Frank R. Bryant ,  Lisa K. Jorgenson

发明人： Tsiu C. Chan ,  Frank R. Bryant ,  Lisa K. Jorgenson

IPC分类号： H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： A method for forming a SRAM structure with polycrystalline P-channel load devices of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A field oxide region is formed over a portion of the substrate. A first gate electrode of a first N-channel field effect device is formed over the substrate having a source/drain region in the substrate. A second gate electrode of a second N-channel field effect device is also formed over the substrate and a portion of the field oxide. A first insulating layer is formed over the integrated circuit containing an opening exposing a portion of the source/drain region and the second gate electrode of the first and second N-channel devices respectively. An interconnect layer having a doped polysilicon layer and a barrier layer is formed over the integrated circuit, patterned and etched to define a shared contact region covering the exposed source/drain region and the second gate electrode of the N-channel devices. A second insulating layer is formed over the integrated circuit having an opening exposing a portion of the interconnect layer. A first conductive layer is formed over the integrated circuit, patterned and etched to define a first and a second gate electrode of a first and a second P-channel field effect device respectively. A gate oxide layer is formed over a portion of the first gate electrode and a portion of the second gate electrode of the first and second P-channel devices. A second conductive layer is formed over the integrated circuit, patterned and etched to define a source/drain and channel region of the first gate electrode of the first P-channel device and covering a portion of the second gate electrode of the second P-channel device.

摘要翻译： 公开了一种用于形成具有集成电路的多晶P沟道负载装置的SRAM结构的方法，以及根据该集成电路形成的集成电路。 在衬底的一部分上形成场氧化物区域。 在衬底上形成第一N沟道场效应器件的第一栅电极，该衬底上具有衬底中的源/漏区。 第二N沟道场效应器件的第二栅电极也形成在衬底和场氧化物的一部分上。 在集成电路上形成第一绝缘层，该集成电路包含分别露出第一和第二N沟道器件的源极/漏极区域和第二栅极电极的一部分的开口。 在集成电路上形成具有掺杂多晶硅层和阻挡层的互连层，被图案化和蚀刻以限定覆盖N沟道器件的暴露的源极/漏极区域和第二栅极电极的共享接触区域。 在集成电路上形成第二绝缘层，该绝缘层具有露出互连层的一部分的开口。 在集成电路上形成第一导电层，被图案化和蚀刻以分别限定第一和第二P沟道场效应器件的第一和第二栅电极。 在第一栅电极的一部分和第一和第二P沟道器件的第二栅电极的一部分上形成栅氧化层。 在集成电路上形成第二导电层，被图案化和蚀刻以限定第一P沟道器件的第一栅电极的源极/漏极和沟道区，并且覆盖第二P沟道的第二栅电极的一部分 设备。

公开(公告)号：US5187114A

公开(公告)日：1993-02-16

申请号：US709630

申请日：1991-06-03

申请人： Tsiu C. Chan ,  Frank R. Bryant

发明人： Tsiu C. Chan ,  Frank R. Bryant

IPC分类号： H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1108

摘要： A method for forming a SRAM structure with polycrystalline P-channel load devices of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A first gate electrode of a first N-channel field effect device is formed over the substrate having a source/drain region in the substrate. A second gate electrode of a second N-channel field effect device is also formed over the substrate and a portion of a field oxide. A metal containing layer is formed over the second gate electrode and the source/drain region of the first N-channel device to define a shared contact region. A first conductive layer is formed over the metal containing layer, patterned and etched to define a first and a second gate electrode of a first and a second P-channel field effect device respectively. A second conductive layer is formed over a portion of the first and second P-channel devices, to define a source/drain and channel region of the P-channel devices.

摘要翻译： 公开了一种用于形成具有集成电路的多晶P沟道负载装置的SRAM结构的方法，以及根据该集成电路形成的集成电路。 在衬底上形成第一N沟道场效应器件的第一栅电极，该衬底上具有衬底中的源/漏区。 第二N沟道场效应器件的第二栅电极也形成在衬底和场氧化物的一部分上。 金属含有层形成在第一N沟道器件的第二栅极电极和源极/漏极区域上，以限定共享接触区域。 第一导电层形成在含金属层之上，被图案化和蚀刻以分别限定第一和第二P沟道场效应器件的第一和第二栅电极。 在第一和第二P沟道器件的一部分上形成第二导电层，以限定P沟道器件的源极/漏极和沟道区。

公开(公告)号：US5116777A

公开(公告)日：1992-05-26

申请号：US516287

申请日：1990-04-30

申请人： Tsiu C. Chan ,  Mehdi Zamanian

发明人： Tsiu C. Chan ,  Mehdi Zamanian

IPC分类号： H01L21/74 ,  H01L27/06 ,  H01L27/105

CPC分类号： H01L21/74 ,  H01L21/743 ,  H01L27/0623 ,  H01L27/105

摘要： An N.sup.+ buried layer is formed under all the N-channel devices in the memory array of an integrated circuit device. The N.sup.+ buried layer can also be formed under N-channel input/output devices. The N.sup.+ buried layers include contacts to the power supply. Such a device layout provides for complete isolation of the memory array from the remainder of the circuitry. The isolation of the N-channel input/output devices also provides for enhanced immunity to input/output noise.

摘要翻译： 在集成电路器件的存储器阵列中的所有N沟道器件下形成N +掩埋层。 N +掩埋层也可以在N沟道输入/输出装置下形成。 N +埋层包括与电源的接触。 这样的器件布局提供了存储器阵列与电路的其余部分的完全隔离。 N沟道输入/输出器件的隔离还提供了增强的输入/输出噪声抗扰度。

公开(公告)号：US5116776A

公开(公告)日：1992-05-26

申请号：US443897

申请日：1989-11-30

申请人： Tsiu C. Chan ,  Frank R. Bryant

发明人： Tsiu C. Chan ,  Frank R. Bryant

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10844 ,  H01L27/10817 ,  H01L28/40 ,  Y10S438/954

摘要： A capacitor suitable for use with a DRAM memory cell is composed of multiple layers of polycrystalline silicon. The storage node is formed from a polycrystalline silicon layer sandwiched between two polysilicon ground plate layers. Such a structure nearly doubles the capacitance for a given chip surface area used. First the bottom polycrystalline silicon plate layer is fabricated, followed by an isolation step and fabrication of the storage node polycrystalline silicon layer. Following another isolation step, the polycrystalline silicon top plate layer is then formed and connected to the bottom plate layer.

摘要翻译： 适用于DRAM存储单元的电容器由多层多晶硅组成。 存储节点由夹在两个多晶硅接地板层之间的多晶硅层形成。 这种结构对于所使用的给定芯片表面积几乎使电容增加一倍。 首先制造底部多晶硅板层，然后进行隔离步骤和存储节点多晶硅层的制造。 在另一隔离步骤之后，然后形成多晶硅顶板层并将其连接到底板层。

公开(公告)号：US4679300A

公开(公告)日：1987-07-14

申请号：US785195

申请日：1985-10-07

申请人： Tsiu C. Chan ,  Yu-Pin Han

发明人： Tsiu C. Chan ,  Yu-Pin Han

IPC分类号： H01L27/04 ,  H01L21/265 ,  H01L21/266 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L29/94

摘要： A method of making a trench capacitor employs an N-type switchable plate formed in a P-type substrate for holding charge at either zero volts or a positive TC voltage and a P-type ground plate that fills in a trench around a memory cell, so that P-type dopant diffuses through a thin oxide insulator to form a channel stop and a pinhold short through the oxide is self-healing by the formation of a reverse-biased P-N diode that cuts off the flow of current through the pinhole.

摘要翻译： 制造沟槽电容器的方法采用形成在P型衬底中的N型可切换板，用于保持零电压或正TC电压的电荷，以及填充存储器单元周围的沟槽的P型接地板， 使得P型掺杂剂通过薄氧化物绝缘体扩散以形成通道阻挡层，并且穿过氧化物的引脚短路通过形成反向偏置PN二极管而自愈，其截止通过针孔的电流流动。

公开(公告)号：US4251876A

公开(公告)日：1981-02-17

申请号：US957587

申请日：1978-11-03

申请人： Vernon G. McKenny ,  Tsiu C. Chan

发明人： Vernon G. McKenny ,  Tsiu C. Chan

IPC分类号： G11C11/412 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3215 ,  H01L23/522 ,  H01L27/11 ,  G11C11/40

CPC分类号： H01L28/20 ,  G11C11/412 ,  H01L21/32055 ,  H01L21/32155 ,  H01L23/522 ,  H01L27/11 ,  H01L27/1112 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A MOSFET random access memory having an extremely low current load memory cell is disclosed. The memory cell comprises a cross-coupled binary stage in which one or more paths to ground can be selectively switched on or off through true and complement data nodes. Impedance means connect a power supply node to the data nodes for charging the data nodes to predetermined voltage levels. The impedance means comprise an intrinsic-extrinsic junction of a substantially pure, intrinsic semiconductor material and a diffusion of extrinsic conductivity impurities disposed within a region of the intrinsic semiconductor material. The impedance means is formed by an isoplanar silicon gate process as an integral portion of a polycrystalline silicon strip which interconnects the power supply node to a data node. A portion of the polycrystalline silicon strip is extended from the data node to form the gate of the transistor to which it is cross-coupled.

摘要翻译： 公开了具有极低电流负载存储单元的MOSFET随机存取存储器。 存储器单元包括交叉耦合二进制级，其中可以通过真实和补码数据节点选择性地打开或关闭一个或多个接地路径。 阻抗意味着将电源节点连接到数据节点，以将数据节点充电到预定的电压电平。 阻抗装置包括基本上纯的本征半导体材料的本征 - 非本征结和设置在本征半导体材料的区域内的外在电导率杂质的扩散。 阻抗装置由等平面硅栅极工艺形成，其是将电源节点与数据节点互连的多晶硅带的整体部分。 多晶硅带的一部分从数据节点延伸以形成与其交叉耦合的晶体管的栅极。