公开(公告)号：US20120001190A1

公开(公告)日：2012-01-05

申请号：US13259154

申请日：2010-02-09

申请人： Tohru Okabe ,  Takeshi Yaneda ,  Tetsuya Aita ,  Tsuyoshi Inoue ,  Yoshiyuki Harumoto

发明人： Tohru Okabe ,  Takeshi Yaneda ,  Tetsuya Aita ,  Tsuyoshi Inoue ,  Yoshiyuki Harumoto

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L21/02532 ,  H01L21/02678 ,  H01L27/1285 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： The invention provides a thin film transistor that can improve its operating speed by improving crystallinity near a bottom surface of a channel layer. Of laser light irradiated onto an amorphous silicon layer, light transmitted through the amorphous silicon layer is absorbed by a gate electrode 130 and thereby produces heat. Since the gate electrode 130 is made of a titanium layer 102 with a low thermal conductivity, the produced heat is less likely to be transmitted through a gate wiring line 110 and dissipated and thus increases the temperature of the gate electrode 130. Radiant heat from the gate electrode 130 is provided to a bottom surface of the amorphous silicon layer and thus the amorphous silicon layer is also heated from its bottom surface. As a result, an amorphous silicon layer 106a melts not only from its top surface but also from its bottom surface and is solidified, whereby crystallization proceeds, and thus, the amorphous silicon layer 106a turns into a polycrystalline silicon layer 106b. Hence, the mobility near a bottom surface of the polycrystalline silicon layer 106b also increases, improving the operating speed of a thin film transistor 100.

摘要翻译： 本发明提供一种薄膜晶体管，其可以通过改善沟道层底表面附近的结晶度来提高其工作速度。 照射到非晶硅层上的激光，透过非晶硅层的光被栅电极130吸收，从而产生热量。 由于栅电极130由具有低热导率的钛层102制成，所产生的热不太可能通过栅极布线110透射并消散，因此增加了栅电极130的温度。来自 栅电极130被提供到非晶硅层的底表面，因此非晶硅层也从其底表面加热。 结果，非晶硅层106a不仅从其顶表面而且从其底表面熔化并且固化，从而进行结晶，因此非晶硅层106a变成多晶硅层106b。 因此，多晶硅层106b的底表面附近的迁移率也增加，提高了薄膜晶体管100的工作速度。

公开(公告)号：US08865516B2

公开(公告)日：2014-10-21

申请号：US13377824

申请日：2010-03-10

申请人： Yoshifumi Ohta ,  Go Mori ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Tetsuya Aita ,  Masahiko Suzuki ,  Okifumi Nakagawa ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Takeshi Hara

发明人： Yoshifumi Ohta ,  Go Mori ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Tetsuya Aita ,  Masahiko Suzuki ,  Okifumi Nakagawa ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Takeshi Hara

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L29/786 ,  H01L29/49 ,  H01L29/66 ,  H01L29/45 ,  G02F1/1368 ,  H01L21/02

CPC分类号： H01L29/22 ,  G02F1/1368 ,  G02F2202/10 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

摘要： The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.

摘要翻译： 本发明提供一种能够实现具有稳定晶体管特性的薄膜晶体管的氧化物半导体，具有由氧化物半导体形成的沟道层的薄膜晶体管及其制造方法，以及配备有该薄膜晶体管的显示装置。 本发明的氧化物半导体是薄膜晶体管的氧化物半导体。 氧化物半导体包括铟，镓，锌和氧作为构成原子，并且氧化物半导体的氧含量为化学计量条件的87％至95％，以原子单位计为100％。

公开(公告)号：US20130193430A1

公开(公告)日：2013-08-01

申请号：US13391638

申请日：2010-03-29

申请人： Yoshifumi Ota ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Takeshi Hara ,  Tetsuya Aita ,  Masahiko Suzuki ,  Okifumi Nakagawa ,  Kazuo Nakagawa ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Hinae Mizuno

发明人： Yoshifumi Ota ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Takeshi Hara ,  Tetsuya Aita ,  Masahiko Suzuki ,  Okifumi Nakagawa ,  Kazuo Nakagawa ,  Yuuji Mizuno ,  Michiko Takei ,  Yoshiyuki Harumoto

IPC分类号： H01L29/786 ,  H01L33/00

CPC分类号： H01L29/7869 ,  G02F1/1368 ,  H01L27/3258 ,  H01L33/0041

摘要： The present invention provides an oxide semiconductor that realizes a TFT excellent in electric properties and process resistance, a TFT comprising a channel layer formed of the oxide semiconductor, and a display device equipped with the TFT. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor, wherein the oxide semiconductor contains Ga (gallium), In (indium), Zn (zinc), and O (oxygen) as constituent atoms, and the oxide semiconductor has Zn atomic composition satisfying the equation of 0.01≦Zn/(In+Zn)≦0.22.

摘要翻译： 本发明提供实现电性能和工艺电阻优异的TFT的氧化物半导体，包括由氧化物半导体形成的沟道层的TFT以及配备有TFT的显示装置。 本发明的氧化物半导体是用于薄膜晶体管的氧化物半导体，其中氧化物半导体包含Ga（镓），In（铟），Zn（锌）和O（氧）作为构成原子，氧化物半导体 具有满足0.01@Zn/（In + Zn）@ 0.22的方程的Zn原子组成。

公开(公告)号：US20130140552A1

公开(公告)日：2013-06-06

申请号：US13581007

申请日：2011-02-22

申请人： Hirohiko Nishiki ,  Yoshimasa Chikama ,  Tetsuya Aita ,  Masahiko Suzuki ,  Michiko Takei ,  Okifumi Nakagawa ,  Yoshiyuki Harumoto ,  Yoshifumi Ohta ,  Takeshi Hara ,  Hinae Mizuno

发明人： Yuuji Mizuno ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Tetsuya Aita ,  Masahiko Suzuki ,  Michiko Takei ,  Okifumi Nakagawa ,  Yoshiyuki Harumoto ,  Yoshifumi Ohta ,  Takeshi Hara

IPC分类号： H01L29/786 ,  H01L29/66

CPC分类号： H01L29/786 ,  H01L29/66742 ,  H01L29/7869 ,  H01L29/78693

摘要： A semiconductor device (100) according to the present invention includes: an oxide semiconductor layer (31) formed on an insulating layer (21), the oxide semiconductor layer (31) containing at least one element selected from the group consisting of In, Zn, and Sn; first and second sacrificial layers (41a) and (41b) formed, with an interspace from each other, on the oxide semiconductor layer (31); a second electrode (52a) formed in contact with an upper face of the first sacrificial layer (41a) and an upper face of the oxide semiconductor layer (31); and a third electrode (52b) formed in contact with an upper face of the second sacrificial layer (41b) and an upper face of the oxide semiconductor layer (31). The first and second sacrificial layers (41a) and (41b) contain an oxide having at least one element selected from the group consisting of Zn, Ga, Mg, Ca, and Sr.

摘要翻译： 根据本发明的半导体器件（100）包括：形成在绝缘层（21）上的氧化物半导体层（31），所述氧化物半导体层（31）包含选自In，Zn ，和Sn; 第一和第二牺牲层（41a）和（41b）在氧化物半导体层（31）上形成有彼此的间隙; 形成为与第一牺牲层（41a）的上表面和氧化物半导体层（31）的上表面接触的第二电极（52a）; 以及与第二牺牲层（41b）的上表面和氧化物半导体层（31）的上表面接触形成的第三电极（52b）。 第一和第二牺牲层（41a）和（41b）含有具有选自Zn，Ga，Mg，Ca和Sr中的至少一种元素的氧化物。

公开(公告)号：US20130105802A1

公开(公告)日：2013-05-02

申请号：US13518566

申请日：2010-12-21

申请人： Yoshiyuki Harumoto ,  Takeshi Hara ,  Tohru Okabe ,  Takeshi Yaneda ,  Tetsuya Aita ,  Tsuyoshi Inoue ,  Michiko Takei

发明人： Yoshiyuki Harumoto ,  Takeshi Hara ,  Tohru Okabe ,  Takeshi Yaneda ,  Tetsuya Aita ,  Tsuyoshi Inoue ,  Michiko Takei

IPC分类号： H01L29/786 ,  H01L33/08 ,  H01L29/66

CPC分类号： H01L29/786 ,  H01L29/04 ,  H01L29/6675 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78678 ,  H01L29/78696 ,  H01L33/08

摘要： The present invention has an object of providing a TFT in which generation of an OFF current is reduced by an efficient manufacturing method. A thin film transistor 100 according to the present invention has a gate electrode 12 formed on a substrate 10, an insulating layer 14 formed on the gate electrode 12, a microcrystalline amorphous silicon layer 18 and an amorphous silicon layer 16 that are formed on the insulating layer 14, a semiconductor layer 20 containing an impurity formed on the amorphous silicon layer 16, and a source electrode 22A and a drain electrode 22B that are formed on the semiconductor layer 20 containing an impurity. The microcrystalline amorphous silicon layer 18 and the semiconductor layer 20 containing an impurity are connected to each other through the amorphous silicon layer 16 without being in direct contact with each other.

摘要翻译： 本发明的目的是提供一种通过有效的制造方法来减少OFF电流的产生的TFT。 根据本发明的薄膜晶体管100具有形成在基板10上的栅电极12，形成在栅电极12上的绝缘层14，形成在绝缘层上的微晶非晶硅层18和非晶硅层16。 层14，包含形成在非晶硅层16上的杂质的半导体层20以及形成在包含杂质的半导体层20上的源电极22A和漏极22B。 含有杂质的微晶非晶硅层18和半导体层20通过非晶硅层16彼此连接而不直接接触。

公开(公告)号：US20130105788A1

公开(公告)日：2013-05-02

申请号：US13393335

申请日：2010-05-06

申请人： Yoshimasa Chikama ,  Hirohiko Nishiki ,  Yoshifumi Ohta ,  Takeshi Hara ,  Okifumi Nakagawa ,  Tetsuya Aita ,  Masahiko Suzuki ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Kazuo Nakagawa ,  Hinae Mizuno

发明人： Yoshimasa Chikama ,  Hirohiko Nishiki ,  Yoshifumi Ohta ,  Yuuji Mizuno ,  Takeshi Hara ,  Okifumi Nakagawa ,  Tetsuya Aita ,  Masahiko Suzuki ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Kazuo Nakagawa

IPC分类号： H01L29/786

CPC分类号： H01L29/786 ,  G02F1/1368 ,  H01L29/7869

摘要： The present invention provides an oxide semiconductor capable of achieving a thin film transistor with excellent electric property and credibility, a thin film transistor having a channel layer formed of the oxide semiconductor, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor, and includes Si, In, Zn, and O as constituent atoms.

摘要翻译： 本发明提供一种能够实现电性能和可靠性优异的薄膜晶体管的氧化物半导体，具有由氧化物半导体形成的沟道层的薄膜晶体管，以及配备有该薄膜晶体管的显示装置。 本发明的氧化物半导体是用于薄膜晶体管的氧化物半导体，并且包括Si，In，Zn和O作为构成原子。

公开(公告)号：US20130099227A1

公开(公告)日：2013-04-25

申请号：US13394343

申请日：2010-04-22

申请人： Okifumi Nakagawa ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Yoshifumi Ohta ,  Takeshi Hara ,  Tetsuya Aita ,  Masahiko Suzuki ,  Kazuo Nakagawa ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Hinae Mizuno

发明人： Okifumi Nakagawa ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Yoshifumi Ohta ,  Takeshi Hara ,  Tetsuya Aita ,  Masahiko Suzuki ,  Kazuo Nakagawa ,  Yuuji Mizuno ,  Michiko Takei ,  Yoshiyuki Harumoto

IPC分类号： H01L29/786

CPC分类号： H01L29/786 ,  G02F1/1368 ,  H01L29/7869

摘要： The present invention provides an oxide semiconductor capable of achieving a thin film transistor with excellent electric property, a thin film transistor having a channel layer formed of the oxide semiconductor, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor, and includes Al, In, Zn, and O as constituent atoms.

摘要翻译： 本发明提供能够实现电性能优异的薄膜晶体管的氧化物半导体，具有由氧化物半导体形成的沟道层的薄膜晶体管，以及配备有薄膜晶体管的显示装置。 本发明的氧化物半导体是用于薄膜晶体管的氧化物半导体，并且包括Al，In，Zn和O作为构成原子。

公开(公告)号：US20130092923A1

公开(公告)日：2013-04-18

申请号：US13521316

申请日：2011-01-12

申请人： Takeshi Hara ,  Hirohiko Nishiki ,  Yoshifumi Ohta ,  Yoshimasa Chikama ,  Tetsuya Aita ,  Masahiko Suzuki ,  Michiko Takei ,  Okifumi Nakagawa ,  Yoshiyuki Harumoto ,  Hinae Mizuno

发明人： Takeshi Hara ,  Hirohiko Nishiki ,  Yoshifumi Ohta ,  Yuuji Mizuno ,  Yoshimasa Chikama ,  Tetsuya Aita ,  Masahiko Suzuki ,  Michiko Takei ,  Okifumi Nakagawa ,  Yoshiyuki Harumoto

IPC分类号： H01L29/786 ,  H01L29/66

CPC分类号： H01L29/786 ,  G02F1/136227 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/1292 ,  H01L29/66742

摘要： An active matrix substrate includes a plurality of pixel electrodes (19a) arranged in a matrix, and a plurality of TFTs (5a) connected to the respective corresponding pixel electrodes (19a). Each TFT (5a) includes a gate electrode (11aa) provided on an insulating substrate (10a), a gate insulating layer (12) covering the gate electrode (11aa), an oxide semiconductor layer (13a) provided on the gate insulating layer (12) over the gate electrode (11aa) and having a channel region (C), and a source electrode (16aa) and a drain electrode (16b) provided on the oxide semiconductor layer (13a), overlapping the gate electrode (11aa) and facing each other with the channel region (C) being interposed between the source and drain electrodes. A protection insulating layer (17) made of a spin-on glass material is provided on the channel region (C) of the oxide semiconductor layer (13a).

摘要翻译： 有源矩阵基板包括以矩阵布置的多个像素电极（19a）和连接到各个相应的像素电极（19a）的多个TFT（5a）。 每个TFT（5a）包括设置在绝缘基板（10a）上的栅电极（11aa），覆盖栅极电极（11aa）的栅极绝缘层（12），设置在栅极绝缘层上的氧化物半导体层 12a）和具有沟道区（C）的栅极电极（11a）和设置在氧化物半导体层（13a）上的源电极（16aa）和漏电极（16b），与栅极电极（11aa）和 沟道区域（C）插入在源极和漏极之间彼此面对。 在氧化物半导体层（13a）的沟道区（C）上设置由旋涂玻璃材料制成的保护绝缘层（17）。

公开(公告)号：US20130023086A1

公开(公告)日：2013-01-24

申请号：US13517079

申请日：2010-08-23

申请人： Yoshimasa Chikama ,  Hiromitsu Katsui ,  Hirohiko Nishiki ,  Yoshifumi Ohta ,  Takeshi Hara ,  Tetsuya Aita ,  Masahiko Suzuki ,  Michiko Takei ,  Okifumi Nakagawa ,  Yoshiyuki Harumoto ,  Hinae Mizuno

发明人： Yoshimasa Chikama ,  Hiromitsu Katsui ,  Hirohiko Nishiki ,  Yoshifumi Ohta ,  Yuuji Mizuno ,  Takeshi Hara ,  Tetsuya Aita ,  Masahiko Suzuki ,  Michiko Takei ,  Okifumi Nakagawa ,  Yoshiyuki Harumoto

IPC分类号： H01L21/336

CPC分类号： H01L27/1225 ,  G02F1/136213 ,  G02F1/1368 ,  G02F2001/13606 ,  G02F2001/136231 ,  G02F2001/136236 ,  G02F2201/501 ,  H01L27/1248 ,  H01L27/1288

摘要： An active matrix substrate includes a plurality of pixel electrodes (P) provided in a matrix, and a plurality of TFTs (5) connected to the pixel electrodes (P). Each of the TFTs (5) includes a gate electrode (11a) provided on an insulating substrate, a gate insulating film (12a) provided to cover the gate electrode (11a), an oxide semiconductor layer (13a) provided on the gate insulating film (12a) to overlap the gate electrode (11a), and a source electrode (17a) and a drain electrode (17b) facing each other and being connected to the oxide semiconductor layer (13a). A protective insulating film (14a) is provided between the oxide semiconductor layer (13a) and the source and drain electrodes (17a) and (17b) to cover the oxide semiconductor layer (13a).

摘要翻译： 有源矩阵基板包括设置在矩阵中的多个像素电极（P）和连接到像素电极（P）的多个TFT（5）。 每个TFT（5）包括设置在绝缘基板上的栅极电极（11a），设置成覆盖栅极电极（11a）的栅极绝缘膜（12a），设置在栅极绝缘膜上的氧化物半导体层 （12a）与栅极电极（11a）重叠，并且与氧化物半导体层（13a）连接的源电极（17a）和漏电极（17b）彼此相对。 在氧化物半导体层（13a）和源极和漏极（17a）和（17b）之间设置保护绝缘膜（14a）以覆盖氧化物半导体层（13a）。

公开(公告)号：US20120138923A1

公开(公告)日：2012-06-07

申请号：US13379670

申请日：2010-04-06

申请人： Takeshi Hara ,  Hirohiko Nishiki ,  Yoshimasa Chikawa ,  Kazuo Nakagawa ,  Yoshifumi Ohta ,  Tetsuya Aita ,  Masahiko Suzuki ,  Okifumi Nakagawa ,  Yoshiyuki Miyajima ,  Yuuji Mizuno ,  Hinae Mizuno ,  Michiko Takei ,  Yoshiyuki Harumoto

发明人： Takeshi Hara ,  Hirohiko Nishiki ,  Yoshimasa Chikawa ,  Kazuo Nakagawa ,  Yoshifumi Ohta ,  Tetsuya Aita ,  Masahiko Suzuki ,  Okifumi Nakagawa ,  Yoshiyuki Miyajima ,  Yuuji Mizuno ,  Hinae Mizuno ,  Michiko Takei ,  Yoshiyuki Harumoto

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1225 ,  H01L29/7869

摘要： The present invention provides a thin film transistor including an oxide semiconductor layer (4) for electrically connecting a signal electrode (6a) and a drain electrode (7a), the an oxide semiconductor layer being made from an oxide semiconductor; and a barrier layer (6b) made from at least one selected from the group consisting of Ti, Mo, W, Nb, Ta, Cr, nitrides thereof, and alloys thereof, the barrier layer (6b) being in touch with the signal electrode (6a) and the oxide semiconductor layer (4) and separating the signal electrode (6a) from the oxide semiconductor layer (4). Because of this configuration, the thin film transistor can form and maintain an ohmic contact between the first electrode and the channel layer, thereby being a thin film transistor with good properties.

摘要翻译： 本发明提供了一种薄膜晶体管，其包括用于电连接信号电极（6a）和漏电极（7a）的氧化物半导体层（4），所述氧化物半导体层由氧化物半导体制成; 以及由选自Ti，Mo，W，Nb，Ta，Cr，氮化物中的至少一种及其合金制成的阻挡层（6b），阻挡层（6b）与信号电极 （6a）和氧化物半导体层（4），并且将信号电极（6a）与氧化物半导体层（4）分离。 由于这种结构，薄膜晶体管可以在第一电极和沟道层之间形成并保持欧姆接触，从而成为具有良好性能的薄膜晶体管。