公开(公告)号：US08306662B2

公开(公告)日：2012-11-06

申请号：US12349873

申请日：2009-01-07

申请人： Sang Yun Kim

发明人： Sang Yun Kim

IPC分类号： G05D1/02

CPC分类号： G01S7/495 ,  G01S17/48 ,  G05D1/0242 ,  G05D2201/0203

摘要： The present invention relates to a position detection device for a mobile robot, including a light-emitting element for emitting light, a light reception element on which light transferred from a bottom, of the light emitted from the light-emitting element and then reflected from an obstacle, is focused, and a signal processing unit for calculating a distance between a position where the light incident on the light reception element is focused and the obstacle. A position detection method using a mobile robot may include operating a robot cleaner, receiving light transferred from a bottom, of light emitted from the robot cleaner and then reflected from an obstacle, and detecting a distance between the robot cleaner and the obstacle from which the light is reflected, determining whether the distance between the robot cleaner and the obstacle increases, and determining whether the robot cleaner has approached the obstacle.

摘要翻译： 本发明涉及一种移动机器人的位置检测装置，其包括发光元件，从发光元件发射的光从底部传输光的光接收元件，然后从 焦点的障碍物和用于计算入射在光接收元件上的光聚焦的位置与障碍物之间的距离的信号处理单元。 使用移动机器人的位置检测方法可以包括操作机器人清洁器，从机器人清洁器发射的光接收从底部传输的光，然后从障碍物反射，并且检测机器人清洁器与障碍物之间的距离， 反射光，确定机器人清洁器与障碍物之间的距离是否增加，以及确定机器人清洁器是否已经靠近障碍物。

公开(公告)号：US07958410B2

公开(公告)日：2011-06-07

申请号：US12216779

申请日：2008-07-10

申请人： Sang-yun Kim ,  Young-don Choi

发明人： Sang-yun Kim ,  Young-don Choi

IPC分类号： G11C29/00

CPC分类号： H04L7/02 ,  H04L7/0337

摘要： A memory chip includes a receiver, a clock phase shifter, an error detector, and a controller. The receiver receives a test signal having a plurality of random data bits. The clock phase shifter shifts the phase of a clock signal to one of first through nth phases (n is a natural number). The controller controls the clock phase shifter to sequentially increase the phase of the clock signal from the first phase when the error detector determines the data bit sampled in synchronization with the clock signal has an erro has an error. The controller controls the clock phase shifter to sequentially decrease the phase of the clock signal from the nth phase when none of the plurality of data bits sampled in synchronization with the clock signal having a kth phase (k is a natural number greater than 1 and smaller than n−1) have an error.

摘要翻译： 存储器芯片包括接收器，时钟移相器，误差检测器和控制器。 接收器接收具有多个随机数据位的测试信号。 时钟移相器将时钟信号的相位移位到第一至第n相之一（n是自然数）。 当误差检测器确定与时钟信号同步采样的数据位具有错误时，控制器控制时钟移相器依次增加来自第一相的时钟信号的相位。 控制器控制时钟移相器，以便在与具有第k相位的时钟信号同步地采样的多个数据位中没有一个（k是大于1和更小的自然数）时，顺序地从第n个相位减小时钟信号的相位 比n-1）有错误。

公开(公告)号：US20090016476A1

公开(公告)日：2009-01-15

申请号：US12216779

申请日：2008-07-10

申请人： Sang-yun Kim ,  Young-don Choi

发明人： Sang-yun Kim ,  Young-don Choi

IPC分类号： H04L7/00

CPC分类号： H04L7/02 ,  H04L7/0337

摘要： A memory chip includes a receiver, a clock phase shifter, an error detector, and a controller. The receiver receives a test signal having a plurality of random data bits. The clock phase shifter shifts the phase of a clock signal to one of first through nth phases (n is a natural number). The controller controls the clock phase shifter to sequentially increase the phase of the clock signal from the first phase when the error detector determines the data bit sampled in synchronization with the clock signal has an erro has an error. The controller controls the clock phase shifter to sequentially decrease the phase of the clock signal from the nth phase when none of the plurality of data bits sampled in synchronization with the clock signal having a kth phase (k is a natural number greater than 1 and smaller than n−1) have an error.

摘要翻译： 存储器芯片包括接收器，时钟移相器，误差检测器和控制器。 接收器接收具有多个随机数据位的测试信号。 时钟移相器将时钟信号的相位移位到第一至第n相之一（n是自然数）。 当误差检测器确定与时钟信号同步采样的数据位具有错误时，控制器控制时钟移相器依次增加来自第一相的时钟信号的相位。 控制器控制时钟移相器，以便在与具有第k相位的时钟信号同步地采样的多个数据位中没有一个（k是大于1和更小的自然数）时，顺序地从第n个相位减小时钟信号的相位 比n-1）有错误。

公开(公告)号：US20080151651A1

公开(公告)日：2008-06-26

申请号：US11836283

申请日：2007-08-09

申请人： Sang-yun Kim ,  Jung-bae Lee ,  Young-don Choi

发明人： Sang-yun Kim ,  Jung-bae Lee ,  Young-don Choi

IPC分类号： G11C7/00

CPC分类号： G11C7/1006

摘要： A semiconductor memory device utilizing a data coding method in an initial operation. The semiconductor memory device includes a plurality of counters communicating with a data coding unit. The counters count the number of data bits and flag information data bits in a first logic state in a first data group which includes at least one data bit and second through nth groups each including at least one data bit and flag information. The data coding unit selectively applies a first operation mode and a second operation mode to each of the first through nth data groups and codes the data of each of the first through nth data groups. The first operation mode codes the data of each of the first through nth data groups such that the counted number of data bits in the first logic state in each of the first through nth groups is minimized. The second operation mode codes the data of each of the first through nth groups such that the difference between the number of data bits and flag information data bits in the first logic state and the number of data bits and flag information data bits in a second logic state in the first through nth data groups is minimized. In this manner, the semiconductor memory device and the associated data coding method prevents the initial logic state of data from being changed due to a voltage drop in the initial operation of the device.

摘要翻译： 一种在初始操作中利用数据编码方法的半导体存储器件。 半导体存储器件包括与数据编码单元通信的多个计数器。 计数器在包括至少一个数据位和第二至第n组的第一数据组中对第一逻辑状态中的数据位和标志信息数据位的数目进行计数，每个包括至少一个数据位和标志信息。 数据编码单元选择性地对第一至第n数据组中的每一个应用第一操作模式和第二操作模式，并对第一至第n数据组中的每一个的数据进行编码。 第一操作模式对第一至第n数据组中的每一个的数据进行编码，使得第一至第n组中的每一个中的第一逻辑状态中的数据位的计数数量最小化。 第二操作模式对第一至第n组中的每一个的数据进行编码，使得第一逻辑状态中的数据位数和标志信息数据位之间的差异以及第二逻辑中的数据位和标志信息数据位的数量 在第一至第n个数据组中的状态被最小化。 以这种方式，半导体存储器件和相关联的数据编码方法防止数据的初始逻辑状态由于器件的初始操作中的电压降而被改变。

公开(公告)号：US20070233319A1

公开(公告)日：2007-10-04

申请号：US11690508

申请日：2007-03-23

申请人： Hyoung-deuk IM ,  Sang-yun KIM

发明人： Hyoung-deuk IM ,  Sang-yun KIM

IPC分类号： G06F19/00

CPC分类号： G05D1/0242 ,  G05D1/0225 ,  G05D2201/0203 ,  G05D2201/0215

摘要： A system is provided for returning a robot to a charger. In this regard, a charger is configured to provide a plurality of docking guide regions by outputting at least one guide signal superposed with at least one other signal to form a return region. Further, the robot is configured to return to the charger at a return speed by detecting the return region.

摘要翻译： 提供了一种将机器人返回到充电器的系统。 在这方面，充电器被配置为通过输出与至少一个其他信号重叠的至少一个引导信号来提供多个对接引导区域以形成返回区域。 此外，机器人被配置为通过检测返回区域以返回速度返回到充电器。

公开(公告)号：US08560120B2

公开(公告)日：2013-10-15

申请号：US12440063

申请日：2007-09-06

申请人： Sang Yun Kim

发明人： Sang Yun Kim

IPC分类号： G05B15/00 ,  G05B19/18

CPC分类号： A47L9/2894 ,  A47L9/2805 ,  A47L9/2842 ,  A47L9/2852 ,  A47L9/2857 ,  A47L9/2889 ,  A47L2201/04 ,  G05D1/0223 ,  G05D1/0242 ,  G05D2201/0203

摘要： A moving robot and its operation method are disclosed. The moving robot includes a moving body/object sensing unit that senses a movement of a human body within a certain distance, a traveling unit that controls a traveling speed and direction, and a controller that outputs a control signal for controlling the traveling speed according to pre-set data to the traveling unit. In a state that the moving robot performs a cleaning operation while moving its locations, when a movement of a human body is sensed by the moving body/object sensing unit, the traveling speed is reduced to allow the user to easily control the external operation, and the efficiency can be increased by utilizing the moving body/object sensing unit for operations of different modes.

摘要翻译： 公开了一种移动机器人及其操作方法。 移动机器人包括感测人体在一定距离内的移动的移动体/物体感测单元，控制行进速度和方向的行驶单元，以及控制器，其根据以下方式输出用于控制行驶速度的控制信号 将预先设定的数据传送到行驶单元。 在移动机器人移动其位置的同时执行清洁操作的状态下，当通过移动体/物体感测单元检测到人体的运动时，减小行驶速度以允许用户容易地控制外部操作， 并且可以通过利用移动体/物体感测单元来进行不同模式的操作来提高效率。

公开(公告)号：US20110182099A1

公开(公告)日：2011-07-28

申请号：US12917832

申请日：2010-11-02

申请人： Sang-yun Kim ,  Tai-young Ko

发明人： Sang-yun Kim ,  Tai-young Ko

IPC分类号： G11C5/02

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C7/02 ,  G11C11/4097

摘要： A semiconductor memory device including: first and second memory cell arrays each including at least one word line, at least three bit lines, and memory cells; and a sense amplifier area disposed between the first and second memory cell arrays and including a sense amplifier circuit for sensing and amplifying data of the memory cells, wherein the at least three bit lines of the first memory cell array and the at least three bit lines of the second memory cell array extend in a first direction and the at least three bit lines of the first and the second memory cell arrays are respectively connected to data lines disposed in a second direction, and wherein a bit line located between two of the at least three bit lines of each of the first and the second memory cell arrays is connected to an outermost data line of the data lines.

摘要翻译： 一种半导体存储器件，包括：第一和第二存储单元阵列，每个包括至少一个字线，至少三个位线和存储单元; 以及设置在第一和第二存储单元阵列之间并包括用于感测和放大存储器单元的数据的读出放大器电路的读出放大器区域，其中第一存储单元阵列的至少三个位线和至少三个位线 的第二存储单元阵列在第一方向上延伸，并且第一和第二存储单元阵列的至少三个位线分别连接到沿第二方向布置的数据线，并且其中位于两个at 第一和第二存储单元阵列中的每一个的至少三条位线连接到数据线的最外层数据线。

公开(公告)号：US20110142368A1

公开(公告)日：2011-06-16

申请号：US12913909

申请日：2010-10-28

申请人： Gun-shik SHIN ,  Dong-hyun KIM ,  Jae-hun LEE ,  Sang-yun KIM

发明人： Gun-shik SHIN ,  Dong-hyun KIM ,  Jae-hun LEE ,  Sang-yun KIM

IPC分类号： G06K9/40

CPC分类号： G06T5/002 ,  G06T2207/20021

摘要： A block-based image denoising method includes determining similarities between a current block and reference blocks within a search range around the current block, from among certain-sized blocks divided from an input image; determining weights of the reference blocks with respect to the current block based on the similarities; and generating resultant blocks by denoising the current block with respect to every block of the input image based on the weights of the reference blocks.

摘要翻译： 基于块的图像去噪方法包括：从当前块与当前块周围的搜索范围内的参考块之间确定与从输入图像分开的特定大小的块中的相似度; 基于相似度确定参考块相对于当前块的权重; 并且基于所述参考块的权重，通过对所述输入图像的每个块去除当前块来生成合成块。

公开(公告)号：US20070096675A1

公开(公告)日：2007-05-03

申请号：US11553224

申请日：2006-10-26

申请人： Sang-yun KIM ,  Young-gie KIM

发明人： Sang-yun KIM ,  Young-gie KIM

IPC分类号： G05D1/00 ,  B64C13/18

CPC分类号： G05D1/0242 ,  G05D1/0225 ,  G05D2201/0203

摘要： Disclosed is a mobile robot charge station return system, which may return a mobile robot to a charge station exactly and rapidly according to a charge station position guidance signal emitted from the charge station. The mobile robot charge station return system includes a charge station for transmitting charge station position guidance signals to different areas in such a way that different emitting distances of the charge station position guidance signals change according to a predetermined time period; and a mobile robot for receiving the charge station position guidance signals, calculating direction and distance information, and returning to the charge station according to the calculated direction and distance information.

摘要翻译： 公开了一种移动机器人充电站返回系统，其可以根据从充电站发出的充电站位置引导信号，将移动机器人精确快速地返回到充电站。 移动机器人充电站返回系统包括：充电站，用于将充电站位置引导信号发送到不同的区域，使得充电站位置引导信号的不同发射距离根据预定的时间段而改变; 以及移动机器人，用于接收充电站位置引导信号，计算方向和距离信息，并根据计算的方向和距离信息返回到充电站。

公开(公告)号：US20130250645A1

公开(公告)日：2013-09-26

申请号：US13897515

申请日：2013-05-20

申请人： Sang-yun Kim ,  Tai-young Ko

发明人： Sang-yun Kim ,  Tai-young Ko

IPC分类号： G11C5/06

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C7/02 ,  G11C11/4097

摘要： A semiconductor memory device including: first and second memory cell arrays each including at least one word line, at least three bit lines, and memory cells; and a sense amplifier area disposed between the first and second memory cell arrays and including a sense amplifier circuit for sensing and amplifying data of the memory cells, wherein the at least three bit lines of the first memory cell array and the at least three bit lines of the second memory cell array extend in a first direction and the at least three bit lines of the first and the second memory cell arrays are respectively connected to data lines disposed in a second direction, and wherein a bit line located between two of the at least three bit lines of each of the first and the second memory cell arrays is connected to an outermost data line of the data lines.

摘要翻译： 一种半导体存储器件，包括：第一和第二存储单元阵列，每个包括至少一个字线，至少三个位线和存储单元; 以及设置在第一和第二存储单元阵列之间并包括用于感测和放大存储器单元的数据的读出放大器电路的读出放大器区域，其中第一存储单元阵列的至少三个位线和至少三个位线 的第二存储单元阵列在第一方向上延伸，并且第一和第二存储单元阵列的至少三个位线分别连接到沿第二方向布置的数据线，并且其中位于两个at 第一和第二存储单元阵列中的每一个的至少三条位线连接到数据线的最外层数据线。