公开(公告)号：US06263448B1

公开(公告)日：2001-07-17

申请号：US09169378

申请日：1998-10-09

申请人： Ely K. Tsern ,  Richard M. Barth ,  Craig E. Hampel ,  Donald C. Stark

发明人： Ely K. Tsern ,  Richard M. Barth ,  Craig E. Hampel ,  Donald C. Stark

IPC分类号： G06F104

CPC分类号： G11C7/22 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3275 ,  G06F9/3869 ,  G11C7/1039 ,  G11C7/1072 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases.

公开(公告)号：US06226754B1

公开(公告)日：2001-05-01

申请号：US09169687

申请日：1998-10-09

申请人： Frederick A. Ware ,  Richard M. Barth ,  Donald C. Stark ,  Craig E. Hampel ,  Ely K. Tsern ,  Abhijit M. Abhyankar

发明人： Frederick A. Ware ,  Richard M. Barth ,  Donald C. Stark ,  Craig E. Hampel ,  Ely K. Tsern ,  Abhijit M. Abhyankar

IPC分类号： G06F104

CPC分类号： G11C7/1072 ,  G11C7/22

摘要： An electronic device with device timing constraints includes a set of connections coupled to an interconnect structure that carries row and column commands. A memory core stores data. A memory interface is connect to the set of connections and the memory core. The memory interface includes circuitry for generating memory core timing signals in accordance with the row commands and the column commands. The memory core timing signals have timing constraints to insure correct memory core operation. The memory interface circuitry includes individual delay components for adjusting the timing of selected timing signals of the memory core timing signals.

摘要翻译： 具有设备定时约束的电子设备包括耦合到承载行和列命令的互连结构的一组连接。 内存核心存储数据。 存储器接口连接到一组连接和存储器核心。 存储器接口包括用于根据行命令和列命令产生存储器核心定时信号的电路。 存储器核心定时信号具有时序约束，以确保正确的存储器核心操作。 存储器接口电路包括用于调整存储器核心定时信号的选定定时信号的定时的各个延迟部件。

公开(公告)号：US6021076A

公开(公告)日：2000-02-01

申请号：US118696

申请日：1998-07-16

申请人： Steven C. Woo ,  Ramprasad Satagopan ,  Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel

发明人： Steven C. Woo ,  Ramprasad Satagopan ,  Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel

IPC分类号： G06F1/20 ,  G06F1/32 ,  G11C7/04 ,  G11C11/406

CPC分类号： G06F1/3225 ,  G06F1/206 ,  G11C11/406 ,  G11C11/40626 ,  Y02B60/1275

摘要： A memory system configured to provide thermal regulation of a plurality of memory devices is disclosed. The memory system comprises a memory device coupled to a bus. Additionally, the memory system also comprises a controller coupled to the bus. The controller determines an operating temperature of the memory device. Based on the operating temperature of the memory device, the controller is further operable to manipulate the operation of the memory system.

摘要翻译： 公开了一种被配置为提供多个存储器件的热调节的存储器系统。 存储器系统包括耦合到总线的存储器件。 此外，存储器系统还包括耦合到总线的控制器。 控制器确定存储器件的工作温度。 基于存储器件的操作温度，控制器还可操作以操纵存储器系统的操作。

公开(公告)号：US5680361A

公开(公告)日：1997-10-21

申请号：US389561

申请日：1995-02-14

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

IPC分类号： G11C7/10 ,  G11C11/401

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/103 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087

摘要： Additional modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

摘要翻译： 提供附加模式以增强存储器系统的功能和性能。 在一个实施例中，向每个列访问中使用的写入数据提供唯一的位掩码。 在替代实施例中，提供位掩码寄存器和字节掩码寄存器以支持位电平和字节电平掩蔽。 位掩码和写数据寄存器被实现为单个寄存器，以提供功能，同时最小化组件空间和成本。 在另一个实施例中，提供单独的位掩码和字节掩码。 字节掩码在一个周期内加载掩码数据，并在下一个“q”列写入访问期间使用。 该结构提供无位掩蔽的操作模式，每行访问提供位掩码，并提供每列访问的位掩码。 为了增强诸如二维图形系统的系统的功能，在替代实施例中，存储器系统具有两个寄存器和选择控制线，以从两个寄存器之一中选择数据。 在计算机图形系统中，用于在前景和背景颜色之间进行选择。 该实施例可以与所描述的其他实施例一起使用以提供增强的功能和性能。

公开(公告)号：US5432823A

公开(公告)日：1995-07-11

申请号：US178601

申请日：1994-01-07

申请人： James A. Gasbarro ,  Mark A. Horowitz ,  Richard M. Barth ,  Winston K. M. Lee ,  Wingyu Leung ,  Paul M. Farmwald

发明人： James A. Gasbarro ,  Mark A. Horowitz ,  Richard M. Barth ,  Winston K. M. Lee ,  Wingyu Leung ,  Paul M. Farmwald

IPC分类号： G06F1/10 ,  G06F1/12 ,  G06F12/00 ,  G06F13/42 ,  G11C11/401 ,  G11C11/407 ,  H04L7/00

CPC分类号： G06F1/10 ,  G06F13/4217 ,  H04L7/0008

摘要： A bus system is described that minimizes clock-data skew. The bus system includes a data bus, a clockline and synchronization circuitry. The clockline has two clockline segments. Each clockline segment extends the entire length of the data bus and is joined to the other clockline segment by a turnaround at one end of the data bus. The clockline ensures that clock and data signals travel in the same direction. Synchronization circuitry within transmitting devices synchronizes data signals to be coupled onto the data bus with the clock signal used by other devices to receive the data.

摘要翻译： 描述了最小化时钟数据偏移的总线系统。 总线系统包括数据总线，时钟线和同步电路。 时钟线有两个时钟线段。 每个时钟线段延伸数据总线的整个长度，并通过数据总线一端的转向连接到另一个时钟线段。 时钟线确保时钟和数据信号沿同一方向行进。 发送设备内的同步电路将数据信号与其他设备使用的时钟信号同步到数据总线上，以接收数据。

公开(公告)号：US5430676A

公开(公告)日：1995-07-04

申请号：US202290

申请日：1994-02-25

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

IPC分类号： G06F13/16 ,  G11C5/06 ,  G11C11/401 ,  G06F12/00

CPC分类号： G11C5/066

摘要： As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.

公开(公告)号：US5337285A

公开(公告)日：1994-08-09

申请号：US65804

申请日：1993-05-21

申请人： Frederick A. Ware ,  James A. Gasbarro ,  John B. Dillon ,  Matthew M. Griffin ,  Richard M. Barth ,  Mark A. Horowitz

发明人： Frederick A. Ware ,  James A. Gasbarro ,  John B. Dillon ,  Matthew M. Griffin ,  Richard M. Barth ,  Mark A. Horowitz

IPC分类号： G06F1/32 ,  G11C5/14 ,  H03K19/00 ,  H03K19/0175 ,  G11C7/00

CPC分类号： G11C5/14

摘要： A power control circuit to minimize power consumption of CMOS circuits by disabling/enabling the clock input to the CMOS circuit. A phase locked loop (PLL) or delay locked loop (DLL) drives a capacitive load of the component and a dummy load comparable to the component load. A standby latch is provided to control the clock input to the component. In a standby state, the clock signal is not provided to the component but the PLL/DLL continues to operate, driving the dummy load. Thus, when it is desirable to power on the circuit, the standby latch is reset and the clock signal is provided to the component, thereby turning on the component with little latency.

摘要翻译： 电源控制电路，通过禁止/使能CMOS电路的时钟输入来最小化CMOS电路的功耗。 锁相环（PLL）或延迟锁定环（DLL）驱动组件的容性负载和与组件负载相当的虚拟负载。 提供备用锁存器来控制对组件的时钟输入。 在待机状态下，时钟信号不提供给组件，但PLL / DLL继续运行，驱动虚拟负载。 因此，当期望对电路通电时，备用锁存器被复位，并且时钟信号被提供给部件，从而以很小的延迟打开部件。

公开(公告)号：US5101417A

公开(公告)日：1992-03-31

申请号：US546456

申请日：1990-06-29

申请人： Edward A. Richley ,  Richard M. Barth

发明人： Edward A. Richley ,  Richard M. Barth

IPC分类号： H04B1/7075

CPC分类号： H04B1/7075 ,  H04B1/70755

摘要： A receiver for a direct sequence spread-spectrum communication system of the type in which a transmitter mixes a clocked pseudo-random sequence with a modulated carrier for spreading the carrier energy across a wide band of frequencies, comprises a resident clock-driven pseudo-random code generator for locally generating an essentially identical, spectrum despreading code sequence; means for clocking the resident code generator at a nominal frequency which is offset in a predetermined sense from the clock frequency of the transmitted code sequence such that the phase of the locally generated code sequence tends to slide in one direction with respect to the phase of the transmitted code sequence; detection means for determining whether the locally generated and the transmitted code sequence are phase aligned or misaligned and for sensing their actual, incipient and/or predicted departures from a phase aligned state, and phase control means for adjusting the clock frequency for the resident code generator whenever such a departure is sensed, thereby shifting the phase of the locally generated code sequence in the opposite direction with respect to the transmitted code sequence by an amount which tends to restore the two code sequences to a phase aligned state.

公开(公告)号：US20120216059A1

公开(公告)日：2012-08-23

申请号：US13406465

申请日：2012-02-27

申请人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

发明人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

IPC分类号： G06F1/32 ,  G06F12/00

CPC分类号： G11C7/1072 ,  G06F1/3225 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4239 ,  G11C7/20 ,  G11C8/12 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2207/2254 ,  Y02D10/151

摘要： Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.

摘要翻译： 在实施例中提供了存储器件和系统的操作方法。 初始化操作在初始化序列期间以第一操作频率进行。 然后在第二操作频率下执行存储器存取操作。 第二个操作频率高于第一个操作频率。 此外，存储器访问操作包括读取操作和写入操作。 在实施例中，从串行存在检测装置读取表示第一操作频率和第二操作频率的信息。

公开(公告)号：US07793039B2

公开(公告)日：2010-09-07

申请号：US12349485

申请日：2009-01-06

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： A semiconductor memory device includes a memory core, a first interface to receive write data from a first set of interconnect resources, and a second interface, separate from the first interface, to receive from a second set of interconnect resources a column address and a first code. The column address is associated with the write data and identifies a column of the memory core in which to store the write data. The first code indicates whether the write data is selectively masked by data mask information. If the first code indicates that the write data is selectively masked, the second interface is to receive data mask information specifying whether to selectively write portions of the write data to the memory core.

摘要翻译： 半导体存储器件包括存储器核，从第一组互连资源接收写数据的第一接口和与第一接口分开的第二接口，以从第二组互连资源接收列地址和第一 码。 列地址与写入数据相关联，并标识存储写入数据的存储器核心的列。 第一代码指示写数据是否被数据掩码信息选择性地屏蔽。 如果第一代码指示写入数据被选择性地屏蔽，则第二接口将接收指定是否选择性地将写数据的部分写入存储器核的数据掩码信息。