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    Non-volatile memory having a reference transistor
    13.
    发明申请
    Non-volatile memory having a reference transistor 有权
    具有参考晶体管的非易失性存储器

    公开(公告)号：US20050041503A1

    公开(公告)日：2005-02-24

    申请号：US10950855

    申请日：2004-09-27

    申请人： Gowrishankar Chindalore ,  Rajesh Rao ,  Jane Yater

    发明人： Gowrishankar Chindalore ,  Rajesh Rao ,  Jane Yater

    IPC分类号： G11C5/00 ,  G11C16/28 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/76

    CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C16/28 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11573

    摘要： A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46). The read control circuit (42) senses a drain current of the reference transistor (46) and adjusts the gate bias voltage to maintain the reference current at a substantially constant value relative to the cell current.

    摘要翻译： 非易失性存储器（30）包括纳米晶体存储单元（50,51,53）。 存储单元晶体管（50,51,53）的编程和擦除阈值电压作为编程/擦除操作的次数增加。 在读取操作期间，参考晶体管（46）提供用于与单元电流进行比较的参考电流。 除了参考晶体管（46）不包括纳米晶体之外，参考晶体管（46）由与制造存储单元晶体管（50,51,53）类似的工艺制成。 通过使用类似的工艺来使参考晶体管（46）和存储单元晶体管（50,51,53）同时工作，参考晶体管（46）的阈值电压将跟踪存储单元晶体管（50）的阈值电压偏移 ，51,53）。 提供读控制电路（42）以偏置参考晶体管（46）的栅极。 读取控制电路（42）感测参考晶体管（46）的漏极电流并调整栅极偏置电压，以使参考电流相对于单元电流保持在基本恒定的值。

    SPLIT GATE MEMORY CELL METHOD
    17.
    发明申请
    SPLIT GATE MEMORY CELL METHOD 有权
    分离栅存储单元方法

    公开(公告)号：US20080182375A1

    公开(公告)日：2008-07-31

    申请号：US11669307

    申请日：2007-01-31

    申请人： Rajesh Rao ,  Ramachandran Muralidhar ,  Leo Mathew

    发明人： Rajesh Rao ,  Ramachandran Muralidhar ,  Leo Mathew

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7923 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/7887

    摘要： A multi-bit split-gate memory device is formed over a substrate. A storage layer is formed over the substrate. A first conductive layer is formed over the storage layer. A thickness of a portion of the conductive layer is removed to leave a pillar of the conductive layer and an area of reduced thickness of the conductive layer. A first sidewall spacer is formed adjacent to the pillar to cover a first portion and a second portion of the area of reduced thickness of the conductive layer. The pillar is replaced with a select gate. The area of reduced thickness is selectively removed to leave the first and second portions as control gates.

    摘要翻译： 在衬底上形成多位分离栅极存储器件。 在衬底上形成存储层。 在存储层上形成第一导电层。 去除导电层的一部分的厚度以留下导电层的柱和导电层的厚度减小的面积。 形成邻近柱的第一侧壁间隔物以覆盖导电层厚度减小区域的第一部分和第二部分。 柱子被一个选择门取代。 选择性地去除厚度减小的区域以留下第一和第二部分作为控制门。

    Method for forming a deposited oxide layer
    18.
    发明申请
    Method for forming a deposited oxide layer 有权
    形成沉积氧化物层的方法

    公开(公告)号：US20070202708A1

    公开(公告)日：2007-08-30

    申请号：US11364128

    申请日：2006-02-28

    申请人： Tien Luo ,  Rajesh Rao

    发明人： Tien Luo ,  Rajesh Rao

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/31612 ,  H01L29/42332 ,  H01L29/7883 ,  H01L29/7885

    摘要： An insulating layer formed by deposition is annealed in the presence of radical oxygen to reduce bond defects. A substrate is provided. An oxide layer is deposited overlying the substrate. The oxide layer has a plurality of bond defects. The oxide layer is annealed in the presence of radical oxygen to modify a substantial portion of the plurality of bond defects by using oxygen atoms. The anneal, in one form, is an in-situ steam generation (ISSG) anneal. In one form, the insulating layer overlies a layer of charge storage material, such as nanoclusters, that form a gate structure of a semiconductor storage device. The ISSG anneal repairs bond defects by oxidizing defective silicon bonds in the oxide layer when the oxide layer is silicon dioxide.

    摘要翻译： 通过沉积形成的绝缘层在自由基氧的存在下退火以减少键合缺陷。 提供基板。 沉积在衬底上的氧化物层。 氧化物层具有多个键合缺陷。 氧化层在自由基氧的存在下进行退火，通过使用氧原子来修饰多个键缺陷的大部分。 一种形式的退火是原位蒸汽发生（ISSG）退火。 在一种形式中，绝缘层覆盖形成半导体存储装置的栅极结构的诸如纳米团簇的电荷存储材料层。 当氧化物层是二氧化硅时，ISSG退火通过氧化氧化物层中的有缺陷的硅键来修复接合缺陷。

    Semiconductor device having nano-pillars and method therefor
    19.
    发明申请
    Semiconductor device having nano-pillars and method therefor 有权
    具有纳米柱的半导体器件及其方法

    公开(公告)号：US20070082495A1

    公开(公告)日：2007-04-12

    申请号：US11244516

    申请日：2005-10-06

    申请人： Leo Mathew ,  Rajesh Rao ,  Ramachandran Muralidhar

    发明人： Leo Mathew ,  Rajesh Rao ,  Ramachandran Muralidhar

    IPC分类号： H01L29/76 ,  H01L21/461 ,  H01L21/302 ,  H01L29/745

    CPC分类号： H01L29/42368 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/32139 ,  H01L28/91 ,  H01L29/512 ,  H01L29/513

    摘要： A semiconductor device includes a plurality of pillars formed from a conductive material. The pillars are formed by using a plurality of nanocrystals as a hardmask for patterning the conductive material. A thickness of the conductive material determines the height of the pillars. Likewise, a width of the pillar is determined by the diameter of a nanocrystal. In one embodiment, the pillars are formed from polysilicon and function as the charge storage region of a non-volatile memory cell having good charge retention and low voltage operation. In another embodiment, the pillars are formed from a metal and function as a plate electrode for a metal-insulator-metal (MIM) capacitor having an increased capacitance without increasing the surface area of an integrated circuit.

    摘要翻译： 半导体器件包括由导电材料形成的多个支柱。 通过使用多个纳米晶体作为用于图案化导电材料的硬掩模来形成柱。 导电材料的厚度决定了支柱的高度。 同样，柱的宽度由纳米晶体的直径决定。 在一个实施例中，柱由多晶硅形成，并且用作具有良好电荷保持和低电压操作的非易失性存储单元的电荷存储区。 在另一个实施例中，支柱由金属形成，并且用作具有增加的电容的金属 - 绝缘体 - 金属（MIM）电容器的平板电极，而不增加集成电路的表面积。

    Method of forming an integrated circuit having nanocluster devices and non-nanocluster devices
    20.
    发明申请
    Method of forming an integrated circuit having nanocluster devices and non-nanocluster devices 有权
    形成具有纳米簇装置和非纳米团簇装置的集成电路的方法

    公开(公告)号：US20060160311A1

    公开(公告)日：2006-07-20

    申请号：US11035913

    申请日：2005-01-14

    申请人： Rajesh Rao ,  Robert Steimle

    发明人： Rajesh Rao ,  Robert Steimle

    IPC分类号： H01L21/8234

    CPC分类号： H01L27/11546 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/105 ,  H01L27/11526 ,  H01L29/785 ,  Y10S438/962 ,  Y10S977/774 ,  Y10S977/943

    摘要： An integrated circuit is formed by identifying multiple regions, each having transistors that have a gate oxide thickness that differs between the multiple regions. One of the regions includes transistors having a nanocluster layer and another of the regions includes transistors with a thin gate oxide used for logic functions. Formation of the gate oxides of the transistors is sequenced based upon the gate oxide thickness and function of the transistors. Thin gate oxides for at least one region of transistors are formed after the formation of gate oxides for the region including the transistors having the nanocluster layer.

    摘要翻译： 通过识别多个区域形成集成电路，每个区域具有在多个区域之间具有不同栅极氧化物厚度的晶体管。 一个区域包括具有纳米团簇层的晶体管，另一个区域包括用于逻辑功能的具有薄栅极氧化物的晶体管。 基于晶体管的栅极氧化物厚度和功能对晶体管的栅氧化物的形成进行排序。 在用于包括具有纳米团簇层的晶体管的区域的栅极氧化物的形成之后，形成晶体管的至少一个区域的薄栅氧化物。