公开(公告)号：US20190042262A1

公开(公告)日：2019-02-07

申请号：US16147506

申请日：2018-09-28

申请人： Michael Espig ,  Bret Toll ,  Raanan Sade ,  Robert Valentine ,  Alexander Heinecke

发明人： Michael Espig ,  Bret Toll ,  Raanan Sade ,  Robert Valentine ,  Alexander Heinecke

IPC分类号： G06F9/38 ,  G06F15/80 ,  G06F9/30

摘要： An apparatus and method for efficient matrix alignment in a systolic array. For example, one embodiment of a processor comprises: a first set of physical tile registers to store first matrix data in rows or columns; a second set of physical tile registers to store second matrix data in rows or columns; a decoder to decode a matrix instruction identifying a first input matrix, a first offset, a second input matrix, and a second offset; and execution circuitry, responsive to the matrix instruction, to read a subset of rows or columns from the first set of physical tile registers in accordance with the first offset, spanning multiple physical tile registers from the first set if indicated by the first offset to generate a first input matrix and the execution circuitry to read a subset of rows or columns from the second set of physical tile registers in accordance with the second offset, spanning multiple physical tile registers from the second set if indicated by the second offset to generate a second input matrix; and the execution circuitry to perform an arithmetic operation with the first and second input matrices in accordance with an opcode of the matrix instruction.

公开(公告)号：US20170177429A1

公开(公告)日：2017-06-22

申请号：US14977354

申请日：2015-12-21

申请人： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

发明人： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC分类号： G06F11/07 ,  G06F3/06

CPC分类号： G06F11/0751 ,  G06F9/38 ,  G06F11/073 ,  G06F12/109 ,  G06F12/145 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/656

摘要： Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US20160283232A1

公开(公告)日：2016-09-29

申请号：US14671569

申请日：2015-03-27

申请人： Raanan Sade ,  Ryan L. Carlson ,  Larisa Novakovsky ,  Erik G. Hallnor ,  Ravi Rajwar ,  Roman Dementiev

发明人： Raanan Sade ,  Ryan L. Carlson ,  Larisa Novakovsky ,  Erik G. Hallnor ,  Ravi Rajwar ,  Roman Dementiev

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30047 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/46

摘要： A processor includes a core and a prefetcher. The prefetcher includes logic to issue a request for data including a requested prefetch. The core includes logic to receive an indication of the request, determine whether the request is for a restricted region of memory, and, based upon whether the request is for the restricted region of memory, allow or deny the request.

摘要翻译： 处理器包括核心和预取器。 预取器包括发出对包括请求的预取的数据的请求的逻辑。 核心包括用于接收请求的指示的逻辑，确定请求是否是针对存储器的受限区域，以及基于该请求是针对该存储器的受限区域，允许还是拒绝该请求。

公开(公告)号：US20150089280A1

公开(公告)日：2015-03-26

申请号：US14038334

申请日：2013-09-26

申请人： Raanan Sade ,  Ron Gabor ,  Deep K. Buch ,  Theodros Yigzaw ,  Stanislav Shwartsman

发明人： Raanan Sade ,  Ron Gabor ,  Deep K. Buch ,  Theodros Yigzaw ,  Stanislav Shwartsman

IPC分类号： G06F11/07

CPC分类号： G06F11/073 ,  G06F11/0793 ,  G06F11/08

摘要： Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.

摘要翻译： 提供了同时处理多个数据错误的机制。 处理设备可以确定在存储器位置范围内的存储器位置中是否发生多个数据错误。 如果多个存储器位置在存储器位置的范围内，则处理设备可以继续恢复过程。 如果多个存储器位置中的一个位于存储器位置的范围之外，则处理设备可以停止恢复过程。

公开(公告)号：US20140122811A1

公开(公告)日：2014-05-01

申请号：US13664682

申请日：2012-10-31

申请人： Stanislav Shwartsman ,  Raanan Sade ,  Larisa Novakovsky ,  Arijit Biswas

发明人： Stanislav Shwartsman ,  Raanan Sade ,  Larisa Novakovsky ,  Arijit Biswas

IPC分类号： G06F12/08

CPC分类号： G06F12/121 ,  G06F11/1064 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/1032 ,  G06T1/20

摘要： A processor includes a core to execute instructions and a cache memory coupled to the core and having a plurality of entries. Each entry of the cache memory may include a data storage including a plurality of data storage portions, each data storage portion to store a corresponding data portion. Each entry may also include a metadata storage to store a plurality of portion modification indicators, each portion modification indicator corresponding to one of the data storage portions. Each portion modification indicator is to indicate whether the data portion stored in the corresponding data storage portion has been modified, independently of cache coherency state information of the entry. Other embodiments are described as claimed.

摘要翻译： 处理器包括执行指令的核心和耦合到核心并且具有多个条目的高速缓存存储器。 高速缓冲存储器的每个条目可以包括包括多个数据存储部分的数据存储部分，每个数据存储部分存储对应的数据部分。 每个条目还可以包括用于存储多个部分修改指示符的元数据存储器，每个部分修改指示符对应于数据存储部分之一。 每个部分修改指示符用于指示存储在相应的数据存储部分中的数据部分是否已被修改，而与条目的高速缓存一致性状态信息无关。 其他实施例被描述为所要求保护的。

公开(公告)号：US08688917B2

公开(公告)日：2014-04-01

申请号：US13355302

申请日：2012-01-20

申请人： Gad Sheaffer ,  Shlomo Raikin ,  Vadim Bassin ,  Raanan Sade ,  Ehud Cohen ,  Oleg Margulis

发明人： Gad Sheaffer ,  Shlomo Raikin ,  Vadim Bassin ,  Raanan Sade ,  Ehud Cohen ,  Oleg Margulis

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/084

摘要： A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item.

公开(公告)号：US08516577B2

公开(公告)日：2013-08-20

申请号：US12887898

申请日：2010-09-22

申请人： Michael S. Bair ,  David W. Burns ,  Robert S. Chappell ,  Prakash Math ,  Leslie A. Ong ,  Pankaj Raghuvanshi ,  Shlomo Raikin ,  Raanan Sade ,  Michael D. Tucknott ,  Igor Yanover

发明人： Michael S. Bair ,  David W. Burns ,  Robert S. Chappell ,  Prakash Math ,  Leslie A. Ong ,  Pankaj Raghuvanshi ,  Shlomo Raikin ,  Raanan Sade ,  Michael D. Tucknott ,  Igor Yanover

IPC分类号： G06F21/00

CPC分类号： G06F9/526

摘要： In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于识别由第一线程执行的原子存储器操作的终止序列的方法，其将定时器与第一线程相关联，并且在完成第一线程之后防止第一线程执行存储器簇操作 原子记忆操作，直到预防窗口过去。 在一些实施例中，该方法可以通过与处理器的存储器执行单元相关联的调节逻辑执行。 描述和要求保护其他实施例。

公开(公告)号：US20200097298A1

公开(公告)日：2020-03-26

申请号：US16140294

申请日：2018-09-24

申请人： CHRISTOPHER J. HUGHES ,  BRET TOLL ,  ALEXANDER HEINECKE ,  DAN BAUM ,  ELMOUSTAPHA OULD-AHMED-VALL ,  RAANAN SADE ,  ROBERT VALENTINE ,  MARK CHARNEY

发明人： CHRISTOPHER J. HUGHES ,  BRET TOLL ,  ALEXANDER HEINECKE ,  DAN BAUM ,  ELMOUSTAPHA OULD-AHMED-VALL ,  RAANAN SADE ,  ROBERT VALENTINE ,  MARK CHARNEY

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F15/80

摘要： An apparatus and method for processing array of structures (AoS) and structure of arrays (SoA) data. For example, one embodiment of a processor comprises: a destination tile register to store data elements in a structure of arrays (SoA) format; a first source tile register to store indices associated with the data elements; instruction fetch circuitry to fetch an array of structures (AoS) gather instruction comprising operands identifying the first source tile register and the destination tile register; a decoder to decode the AoS gather instruction; and execution circuitry to determine a plurality of system memory addresses based on the indices from the first source tile register, to read data elements from the system memory addresses in an AoS format, and to load the data elements to the destination tile register in an SoA format.

公开(公告)号：US20190042245A1

公开(公告)日：2019-02-07

申请号：US16146854

申请日：2018-09-28

申请人： Bret TOLL ,  Alexander F. HEINECKE ,  Christopher J. HUGHES ,  Ronen ZOHAR ,  Michael ESPIG ,  Dan BAUM ,  Raanan SADE ,  Robert VALENTINE

发明人： Bret TOLL ,  Alexander F. HEINECKE ,  Christopher J. HUGHES ,  Ronen ZOHAR ,  Michael ESPIG ,  Dan BAUM ,  Raanan SADE ,  Robert VALENTINE

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06

摘要： Disclosed embodiments relate to instructions for fast element unpacking. In one example, a processor includes fetch circuitry to fetch an instruction whose format includes fields to specify an opcode and locations of an Array-of-Structures (AOS) source matrix and one or more Structure of Arrays (SOA) destination matrices, wherein: the specified opcode calls for unpacking elements of the specified AOS source matrix into the specified Structure of Arrays (SOA) destination matrices, the AOS source matrix is to contain N structures each containing K elements of different types, with same-typed elements in consecutive structures separated by a stride, the SOA destination matrices together contain K segregated groups, each containing N same-typed elements, decode circuitry to decode the fetched instruction, and execution circuitry, responsive to the decoded instruction, to unpack each element of the specified AOS matrix into one of the K element types of the one or more SOA matrices.

公开(公告)号：US20170286121A1

公开(公告)日：2017-10-05

申请号：US15089095

申请日：2016-04-01

申请人： Gur HILDESHEIM ,  Igor YANOVER ,  Stanislav SHWARTSMAN ,  Raanan SADE ,  Ron RAIS

发明人： Gur HILDESHEIM ,  Igor YANOVER ,  Stanislav SHWARTSMAN ,  Raanan SADE ,  Ron RAIS

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/3836 ,  G06F9/3859

摘要： An apparatus and method are described for at-retirement re-execution of faulting operations. For example, one embodiment of a processor comprises: an out-of-order engine to schedule and dispatch operations to an execution unit at least some of the operations comprising load operations to load data from a system memory and store operations to store data to the system memory; a first circuit to determine whether a current load/store operation is at retirement; a second circuit to cause logging circuitry and/or fault registers to be active when a load/store operation has been dispatched at retirement, wherein upon detection of a fault condition associated with the load/store operation, data associated with the fault is to be written to the logging circuitry and/or fault registers, the second circuit to cause the logging circuitry and/or fault registers to be inactive if the load/store operation has not be dispatched at retirement.