公开(公告)号：US20190042245A1

公开(公告)日：2019-02-07

申请号：US16146854

申请日：2018-09-28

申请人： Bret TOLL ,  Alexander F. HEINECKE ,  Christopher J. HUGHES ,  Ronen ZOHAR ,  Michael ESPIG ,  Dan BAUM ,  Raanan SADE ,  Robert VALENTINE

发明人： Bret TOLL ,  Alexander F. HEINECKE ,  Christopher J. HUGHES ,  Ronen ZOHAR ,  Michael ESPIG ,  Dan BAUM ,  Raanan SADE ,  Robert VALENTINE

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06

摘要： Disclosed embodiments relate to instructions for fast element unpacking. In one example, a processor includes fetch circuitry to fetch an instruction whose format includes fields to specify an opcode and locations of an Array-of-Structures (AOS) source matrix and one or more Structure of Arrays (SOA) destination matrices, wherein: the specified opcode calls for unpacking elements of the specified AOS source matrix into the specified Structure of Arrays (SOA) destination matrices, the AOS source matrix is to contain N structures each containing K elements of different types, with same-typed elements in consecutive structures separated by a stride, the SOA destination matrices together contain K segregated groups, each containing N same-typed elements, decode circuitry to decode the fetched instruction, and execution circuitry, responsive to the decoded instruction, to unpack each element of the specified AOS matrix into one of the K element types of the one or more SOA matrices.

公开(公告)号：US20160179544A1

公开(公告)日：2016-06-23

申请号：US14580999

申请日：2014-12-23

申请人： Alexander F. Heinecke ,  Christopher J. Hughes ,  Daehyun Kim ,  Jong Soo Park

发明人： Alexander F. Heinecke ,  Christopher J. Hughes ,  Daehyun Kim ,  Jong Soo Park

IPC分类号： G06F9/38 ,  G06F9/30

摘要： A processor includes a core, a hardware prefetcher, and a prefetcher control module. The hardware prefetcher includes logic to make speculative prefetch requests, through a memory subsystem, for elements for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to selectively suppress, based on a hardware-prefetch suppression instruction executed by the core, a speculative prefetch request to be made by the hardware prefetcher.

摘要翻译： 处理器包括核心，硬件预取器和预取器控制模块。 硬件预取器包括用于通过存储器子系统进行推测预取请求的逻辑，用于由核心执行的元素以及将预取元素存储在高速缓存中的逻辑。 预取器控制模块包括用于基于由核心执行的硬件预取抑制指令来选择性地抑制由硬件预取器进行的推测预取请求的逻辑。