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    MANUFACTURING METHOD FOR METAL GATE
    12.
    发明申请
    MANUFACTURING METHOD FOR METAL GATE 有权
    金属门的制造方法

    公开(公告)号：US20130023098A1

    公开(公告)日：2013-01-24

    申请号：US13184572

    申请日：2011-07-18

    Applicant: Po-Cheng Huang ,  Kuo-Chih Lai ,  Ching-I Li ,  Yu-Shu Lin ,  Ya-Jyuan Hung ,  Yen-Liang Lu ,  Yu-Wen Wang ,  Hsin-Chih Yu

    Inventor： Po-Cheng Huang ,  Kuo-Chih Lai ,  Ching-I Li ,  Yu-Shu Lin ,  Ya-Jyuan Hung ,  Yen-Liang Lu ,  Yu-Wen Wang ,  Hsin-Chih Yu

    IPC: H01L21/336

    CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833

    Abstract: A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.

    Abstract translation: 金属栅极的制造方法包括提供具有形成在其上的电介质层和多晶硅层的基板，多晶硅层，在多晶硅层上形成保护层，在保护层上形成图案化的硬掩模，进行第一蚀刻工艺 蚀刻保护层和多晶硅层，以在衬底上形成具有第一高度的虚拟栅极，形成覆盖图案化硬掩模和伪栅极的多层介电结构，去除伪栅极以在衬底上形成栅极沟槽， 以及在所述栅极沟槽中形成具有第二高度的金属栅极。 金属栅极的第二高度基本上等于虚拟栅极的第一高度。

    POLY OPENING POLISH PROCESS
    13.
    发明申请
    POLY OPENING POLISH PROCESS 有权

    公开(公告)号：US20120322265A1

    公开(公告)日：2012-12-20

    申请号：US13162776

    申请日：2011-06-17

    Applicant: Chun-Wei HSU ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

    Inventor： Chun-Wei HSU ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

    IPC: H01L21/304 ,  H01L21/306

    CPC classification number: H01L21/31053 ,  H01L21/02065 ,  H01L29/517 ,  H01L29/66545

    Abstract: A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.

    Abstract translation: 多孔抛光工艺包括以下步骤。 提供半成品半导体元件。 半成品半导体部件包括基板，设置在基板上的栅极和设置在基板上并覆盖栅极的电介质层。 将第一抛光工艺施加到电介质层上。 第二次抛光工艺应用于浇口。 第二抛光工艺利用包含水溶性聚合物表面活性剂，碱性化合物和水的润湿溶液。 多孔抛光工艺可有效去除化学机械抛光中形成的氧化物残留物，从而提高集成电路的性能，降低集成电路的生产成本。

    Poly opening polish process
    16.
    发明授权
    Poly opening polish process 有权
    多开口抛光工艺

    公开(公告)号：US08513128B2

    公开(公告)日：2013-08-20

    申请号：US13162776

    申请日：2011-06-17

    Applicant: Chun-Wei Hsu ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

    Inventor： Chun-Wei Hsu ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

    IPC: H01L21/304 ,  H01L21/306 ,  B44C1/22

    CPC classification number: H01L21/31053 ,  H01L21/02065 ,  H01L29/517 ,  H01L29/66545

    Abstract: A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.

    Abstract translation: 多孔抛光工艺包括以下步骤。 提供半成品半导体元件。 半成品半导体部件包括基板，设置在基板上的栅极和设置在基板上并覆盖栅极的电介质层。 将第一抛光工艺施加到电介质层上。 第二次抛光工艺应用于浇口。 第二抛光工艺利用包含水溶性聚合物表面活性剂，碱性化合物和水的润湿溶液。 多孔抛光工艺可有效去除化学机械抛光中形成的氧化物残留物，从而提高集成电路的性能，降低集成电路的生产成本。

    Manufacturing method for metal gate
    17.
    发明授权
    Manufacturing method for metal gate 有权
    金属门制造方法

    公开(公告)号：US08486790B2

    公开(公告)日：2013-07-16

    申请号：US13184572

    申请日：2011-07-18

    Applicant: Po-Cheng Huang ,  Kuo-Chih Lai ,  Ching-I Li ,  Yu-Shu Lin ,  Ya-Jyuan Hung ,  Yen-Liang Lu ,  Yu-Wen Wang ,  Hsin-Chih Yu

    Inventor： Po-Cheng Huang ,  Kuo-Chih Lai ,  Ching-I Li ,  Yu-Shu Lin ,  Ya-Jyuan Hung ,  Yen-Liang Lu ,  Yu-Wen Wang ,  Hsin-Chih Yu

    IPC: H01L21/336

    CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833

    Abstract: A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.

    Abstract translation: 金属栅极的制造方法包括提供具有形成在其上的电介质层和多晶硅层的基板，多晶硅层，在多晶硅层上形成保护层，在保护层上形成图案化的硬掩模，进行第一蚀刻工艺 蚀刻保护层和多晶硅层，以在衬底上形成具有第一高度的虚拟栅极，形成覆盖图案化硬掩模和伪栅极的多层介电结构，去除伪栅极以在衬底上形成栅极沟槽， 以及在所述栅极沟槽中形成具有第二高度的金属栅极。 金属栅极的第二高度基本上等于虚拟栅极的第一高度。

    SEMICONDUCTOR PROCESS
    18.
    发明申请
    SEMICONDUCTOR PROCESS 有权
    半导体工艺

    公开(公告)号：US20130052825A1

    公开(公告)日：2013-02-28

    申请号：US13220692

    申请日：2011-08-30

    Applicant: Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chun-Wei Hsu ,  Yen-Ming Chen ,  Chih-Hsun Lin ,  Chang-Hung Kung

    Inventor： Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chun-Wei Hsu ,  Yen-Ming Chen ,  Chih-Hsun Lin ,  Chang-Hung Kung

    IPC: H01L21/306

    CPC classification number: H01L21/3212 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/7684 ,  H01L21/823835 ,  H01L29/665

    Abstract: A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.

    Abstract translation: 半导体工艺包括以下步骤。 第一栅极结构和第二栅极结构形成在基板上，其中第一栅极结构的顶部包括盖层，使得第一栅极结构的垂直高度高于第二栅极结构的垂直高度。 在基板上形成介电层。 执行第一化学机械抛光工艺以暴露盖层的顶表面。 执行第二化学机械抛光工艺以暴露第二栅极结构的顶表面，或执行蚀刻工艺以去除位于第二栅极结构上的介电层。 然后执行第二化学机械抛光工艺以除去盖层。

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