公开(公告)号：US09076818B2

公开(公告)日：2015-07-07

申请号：US13528257

申请日：2012-06-20

Applicant: Andreas Kurz ,  Peter Javorka ,  Sergej Mutas ,  Clemens Wündisch

Inventor： Andreas Kurz ,  Peter Javorka ,  Sergej Mutas ,  Clemens Wündisch

IPC: H01L21/4763 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/6659 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device includes forming first and second gate structures overlying the semiconductor substrate, and depositing a layer of a silicide-resistant material over the first and second gate structures and over the semiconductor substrate. The method further includes forming sidewall spacers from the layer of silicide-resistant material adjacent the first gate structure and removing the silicide-resistant material adjacent the sidewall spacers to expose the silicon substrate in a source and drain region. Still further, the method includes implanting conductivity determining impurities in the source and drain region, depositing a silicide forming metal, and annealing the semiconductor device to form a silicide in the source and drain region. The silicide-resistant material is not removed from over the second gate structure so as to prevent silicide formation at the second gate structure.

Abstract translation: 一种用于制造半导体器件的方法包括形成覆盖半导体衬底的第一和第二栅极结构，以及在第一和第二栅极结构之上以及半导体衬底之上沉积耐硅材料层。 该方法还包括从与第一栅极结构相邻的耐硅化物材料层形成侧壁间隔物，并移除邻近侧壁间隔物的耐硅化物材料，以在源极和漏极区域露出硅衬底。 此外，该方法包括在源极和漏极区域中注入电导率确定杂质，沉积形成硅化物的金属，以及退火半导体器件以在源极和漏极区域中形成硅化物。 不会从第二栅极结构上除去耐硅化物质，以防止在第二栅极结构处形成硅化物。

公开(公告)号：US20130221478A1

公开(公告)日：2013-08-29

申请号：US13405713

申请日：2012-02-27

Applicant: Stephan Kronholz ,  Jorg Radecker ,  Hans-Juergen Thees ,  Peter Javorka

Inventor： Stephan Kronholz ,  Jorg Radecker ,  Hans-Juergen Thees ,  Peter Javorka

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76232

Abstract: Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices using a spin-on glass material or a flowable oxide material. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure comprised of an insulating material in at least the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench.

Abstract translation: 本文公开了用于使用旋涂玻璃材料或可流动氧化物材料的半导体器件形成隔离结构（例如沟槽隔离结构）的各种方法。 在一个示例中，该方法包括在半导体衬底中形成沟槽，在至少沟槽中形成由绝缘材料构成的下隔离结构，其中下隔离结构具有位于衬底上表面下方的上表面， 以及在所述下隔离结构之上形成上隔离结构，其中所述上隔离结构的一部分位于所述沟槽内。

公开(公告)号：US20130178045A1

公开(公告)日：2013-07-11

申请号：US13348101

申请日：2012-01-11

Applicant: Chung Foong Tan ,  Maciej Wiatr ,  Peter Javorka ,  Falong Zhou

Inventor： Chung Foong Tan ,  Maciej Wiatr ,  Peter Javorka ,  Falong Zhou

IPC: H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L21/76232 ,  H01L29/42376

Abstract: Methods of forming transistor devices having an increased gate width dimension are disclosed. In one example, the method includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active region in the substrate, performing an ion implantation process on the isolation structure to create a damaged region in the isolation structure and, after performing the implantation process, performing an etching process to remove at least a portion of the damaged region to define a recess in the isolation structure, wherein a portion of the recess extends below an upper surface of the substrate and exposes a sidewall of the active region. The method further includes forming a gate insulation layer above the active region, wherein a portion of the insulation layer extends into the recess, and forming a gate electrode above the insulation layer, wherein a portion of the gate electrode extends into the recess.

Abstract translation: 公开了具有增加的栅极宽度尺寸的晶体管器件的形成方法。 在一个示例中，该方法包括在半导体衬底中形成隔离结构，其中隔离结构限定衬底中的有源区，在隔离结构上执行离子注入工艺以在隔离结构中产生受损区域，并且在执行 所述注入工艺，执行蚀刻工艺以去除所述损坏区域的至少一部分以在所述隔离结构中限定凹部，其中所述凹部的一部分在所述衬底的上表面下方延伸并暴露所述有源区的侧壁。 该方法还包括在有源区上方形成栅极绝缘层，其中绝缘层的一部分延伸到凹槽中，并在绝缘层之上形成栅电极，其中栅电极的一部分延伸到凹槽中。

公开(公告)号：US20130032864A1

公开(公告)日：2013-02-07

申请号：US13204271

申请日：2011-08-05

Applicant: Peter Javorka ,  Stephan D. Kronholz ,  Matthias Kessler ,  Roman Boschke

Inventor： Peter Javorka ,  Stephan D. Kronholz ,  Matthias Kessler ,  Roman Boschke

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/6653 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Devices are formed with boot shaped source/drain regions formed by isotropic etching followed by anisotropic etching. Embodiments include forming a gate on a substrate, forming a first spacer on each side of the gate, forming a source/drain region in the substrate on each side of the gate, wherein each source/drain region extends under a first spacer, but is separated therefrom by a portion of the substrate, and has a substantially horizontal bottom surface. Embodiments also include forming each source/drain region by forming a cavity to a first depth adjacent the first spacer and forming a second cavity to a second depth below the first cavity and extending laterally underneath the first spacers.

Abstract translation: 器件形成有通过各向同性蚀刻然后进行各向异性蚀刻形成的引线形状的源极/漏极区域。 实施例包括在衬底上形成栅极，在栅极的每一侧上形成第一间隔物，在栅极的每一侧上在衬底中形成源极/漏极区域，其中每个源极/漏极区域在第一间隔物之下延伸，但是 由基板的一部分与之隔开，并具有基本上水平的底面。 实施例还包括通过将空腔形成为与第一间隔件相邻的第一深度并形成第二腔至第一腔的第二深度并且在第一间隔物下方横向延伸来形成每个源/漏区。

公开(公告)号：US08338892B2

公开(公告)日：2012-12-25

申请号：US12893808

申请日：2010-09-29

Applicant: Stephan Kronholz ,  Roman Boschke ,  Maciej Wiatr ,  Peter Javorka

Inventor： Stephan Kronholz ,  Roman Boschke ,  Maciej Wiatr ,  Peter Javorka

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/26586 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/82385 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845

Abstract: In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage.

Abstract translation: 在MOS晶体管元件中，通过施加减小的宽度的间隔结构，应变诱导半导体合金可以嵌入在有源区中，并且与沟道区的偏移减小。 为了降低在栅极电极结构的顶部区域产生半导体残留物的可能性，可以引入半导体材料的一定程度的角圆化，这可以在外延生长应变诱导半导体之前通过离子注入来实现 材料。 这个概念可以有利地结合提供在早期制造阶段中提供的复杂的高k金属栅电极。

公开(公告)号：US20120305995A1

公开(公告)日：2012-12-06

申请号：US13483481

申请日：2012-05-30

Applicant: Peter Javorka ,  Stephan Kronholz ,  Gunda Beernink

Inventor： Peter Javorka ,  Stephan Kronholz ,  Gunda Beernink

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834

Abstract: In sophisticated semiconductor devices, transistors may be formed on the basis of a high-k metal gate electrode structure provided in an early manufacturing phase, wherein an efficient strain-inducing mechanism may be implemented by using an embedded strain-inducing semiconductor alloy. In order to reduce the number of lattice defects and provide enhanced etch resistivity in a critical zone, i.e., in a zone in which a threshold voltage adjusting semiconductor alloy and the strain-inducing semiconductor material are positioned in close proximity, an efficient buffer material or seed material, such as a silicon material, is incorporated, which may be accomplished during the selective epitaxial growth process.

Abstract translation: 在复杂的半导体器件中，可以在早期制造阶段提供的高k金属栅电极结构的基础上形成晶体管，其中可以通过使用嵌入式应变诱导半导体合金来实现有效的应变诱导机制。 为了减少晶格缺陷的数量并且在临界区域（即，阈值电压调节半导体合金和应变诱导半导体材料位于紧邻的区域）提供增强的蚀刻电阻率，可以使用有效的缓冲材料或 引入种子材料，例如硅材料，其可以在选择性外延生长过程期间完成。

公开(公告)号：US20120202326A1

公开(公告)日：2012-08-09

申请号：US13020369

申请日：2011-02-03

Applicant: Stephan-Detlef KRONHOLZ ,  Peter JAVORKA ,  Roman BOSCHKE

Inventor： Stephan-Detlef KRONHOLZ ,  Peter JAVORKA ,  Roman BOSCHKE

IPC: H01L21/311 ,  H01L21/8238

CPC classification number: H01L21/31155 ,  H01L21/31111 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864

Abstract: Embodiments of methods for fabricating the semiconductor devices are provided. The method includes forming a layer of spacer material over a semiconductor region that includes a first gate electrode structure and a second gate electrode structure. Carbon is introduced into a portion of the layer covering the semiconductor region about the first gate electrode structure or the second gate electrode structure. The layer is etched to form a first sidewall spacer about the first gate electrode structure and a second sidewall spacer about the second gate electrode structure.

Abstract translation: 提供了制造半导体器件的方法的实施例。 该方法包括在包括第一栅电极结构和第二栅电极结构的半导体区上形成间隔物层。 将碳引入围绕第一栅电极结构或第二栅电极结构覆盖半导体区的层的一部分。 蚀刻该层以围绕第一栅极电极结构形成第一侧壁隔离物，并围绕第二栅电极结构形成第二侧壁隔离物。

公开(公告)号：US20120161250A1

公开(公告)日：2012-06-28

申请号：US13198209

申请日：2011-08-04

Applicant: Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

Inventor： Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823814

Abstract: When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage on the basis of a silicon/germanium semiconductor alloy for adjusting appropriate electronic conditions in the channel region, the efficiency of a strain-inducing embedded semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by initiating a crystal growth in the silicon material of the gate electrode structure after the gate patterning process. In this manner, the negative strain of the threshold voltage adjusting silicon/germanium alloy may be reduced or compensated for.

Abstract translation: 当在硅/锗半导体合金的基础上在早期制造阶段形成复杂的高k金属栅极电极结构以调整沟道区域中适当的电子条件时，应变诱导嵌入式半导体合金如硅 /锗合金，可以通过在栅极图案化工艺之后在栅电极结构的硅材料中引发晶体生长来增强。 以这种方式，可以减小或补偿阈值电压调节硅/锗合金的负应变。

公开(公告)号：US07897451B2

公开(公告)日：2011-03-01

申请号：US12123524

申请日：2008-05-20

Applicant: Maciej Wiatr ,  Casey Scott ,  Andreas Gehring ,  Peter Javorka ,  Andy Wei

Inventor： Maciej Wiatr ,  Casey Scott ,  Andreas Gehring ,  Peter Javorka ,  Andy Wei

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/1079 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7848

Abstract: By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the crystalline state of the P-channel transistors while annealing the N-channel transistors in the presence of an appropriate material layer which may not to be patterned prior to the anneal process, thereby avoiding additional lithography and masking steps.

Abstract translation: 通过选择性地对N沟道晶体管施加应力记忆技术，可以实现晶体管性能的显着改善。 在施加应力记忆方法时的高选择性可以通过在存在可在退火工艺之前不被图案化的适当材料层的情况下退火N沟道晶体管的同时基本上保持P沟道晶体管的结晶状态来实现， 从而避免了额外的光刻和掩蔽步骤。

公开(公告)号：US07696052B2

公开(公告)日：2010-04-13

申请号：US11558006

申请日：2006-11-09

Applicant: Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann ,  Peter Javorka ,  Joe Bloomquist

Inventor： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann ,  Peter Javorka ,  Joe Bloomquist

IPC: H01L21/336

CPC classification number: H01L29/66628 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/78684

Abstract: By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism.

Abstract translation: 通过凹陷漏极和源极区域，可以在凹部中形成诸如接触蚀刻停止层的高应力层，以增强场效应晶体管的相邻沟道区域中的应变产生。 此外，应变半导体材料可以通过减少或避免金属硅化物的不适当的松弛效应来定位在靠近沟道区域，从而也为应变产生提供增强的效率。 在一些方面，两种效应可以组合以获得更有效的应变诱导机制。