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公开(公告)号：US07285827B1
公开(公告)日：2007-10-23
申请号：US11194449
申请日：2005-08-02
Applicant: Yi He , Zhizheng Liu , Meng Ding , Wei Zheng
Inventor： Yi He , Zhizheng Liu , Meng Ding , Wei Zheng
IPC: H01L23/62
CPC classification number: H01L27/0266 , H01L27/0255
Abstract: A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN or PNP diode reduces device damage and performance impairment that may result from device charging by drawing charges away from the memory device.
Abstract translation: 一种设备包括存储器件和耦合到存储器件的字线的NPN或PNP二极管。 NPN或PNP二极管通过从存储器件中抽取电荷来减少设备充电所造成的器件损坏和性能损害。
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公开(公告)号：US20070223148A1
公开(公告)日：2007-09-27
申请号：US11745787
申请日：2007-05-08
Applicant: Meng Ding , Surya Pattanaik , Chie Poon , Neil Robertson
Inventor： Meng Ding , Surya Pattanaik , Chie Poon , Neil Robertson
IPC: G11B5/33
CPC classification number: G11B5/11 , B23K1/0056 , B23K1/018 , B23K26/0622 , B23K26/354 , B23K2101/42 , G11B5/3906 , G11B5/40
Abstract: A device according to one embodiment includes an electronic component such as an MR sensor, a pair of leads operatively coupled to the electronic component, and shorting material between the leads, the shorting material having been applied by a laser deposition process, the shorting material having been severed. A magnetic storage system according to another embodiment includes magnetic media; and at least one head for reading from and writing to the magnetic media, each head having: a sensor; and a writer coupled to the sensor. The system also includes a pair of pads or leads operatively coupled to the head; shorting material between the leads, the shorting material having been applied by a laser deposition process, the shorting material having been severed; a slider for supporting the head; and a control unit coupled to the head for controlling operation of the head.
Abstract translation: 根据一个实施例的装置包括诸如MR传感器的电子部件，可操作地耦合到电子部件的一对引线以及引线之间的短路材料，通过激光沉积工艺施加了短路材料，所述短路材料具有 被切断 根据另一实施例的磁存储系统包括磁介质; 以及用于从磁介质读取和写入至少一个头部，每个头部具有：传感器; 以及耦合到传感器的写入器。 该系统还包括可操作地耦合到头部的一对垫或引线; 在引线之间短路材料，通过激光沉积工艺施加的短路材料，短路材料已被切断; 用于支撑头部的滑块; 以及耦合到头部用于控制头部的操作的控制单元。
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公开(公告)号：US07062838B2
公开(公告)日：2006-06-20
申请号：US10666679
申请日：2003-09-19
Applicant: Meng Ding , Kuok San Ho , Tsann Lin , Huey-Ming Tzeng
Inventor： Meng Ding , Kuok San Ho , Tsann Lin , Huey-Ming Tzeng
CPC classification number: B24B37/013 , B24B49/10 , G11B5/39 , Y10T29/49041 , Y10T29/49046 , Y10T29/49048
Abstract: A method of forming an embedded read element is used in the fabrication process of a magnetic head assembly including write and read heads. In this method, three photolithographic patterning steps are applied for defining the designed height of the embedded read element, defining its designed width, and connecting it with conducting layers, respectively. An in-line lapping guide is also formed with a spacing in front of the embedded read element. In this method, two mechanical lapping steps are applied, one monitored by measuring the resistance of a parallel circuit of the embedded read element and the in-line lapping guide, and the other monitored by measuring the GMR response of the embedded read element.
Abstract translation: 在包括写入和读取头的磁头组件的制造过程中使用形成嵌入式读取元件的方法。 在该方法中，应用三个光刻图案步骤来定义嵌入式读取元件的设计高度，限定其设计宽度，并将其与导电层连接。 在嵌入式读取元件的前面还形成有间距的在线研磨引导件。 在这种方法中，应用了两个机械研磨步骤，一个通过测量嵌入式读取元件的并联电路的电阻和在线研磨导轨进行监测，另一个通过测量嵌入式读取元件的GMR响应进行监测。
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公开(公告)号：US08809936B2
公开(公告)日：2014-08-19
申请号：US11461428
申请日：2006-07-31
Applicant: Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
Inventor： Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
IPC: H01L29/788
CPC classification number: H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/513
Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.
Abstract translation: 提供一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，在电荷陷阱层上形成第二绝缘体层，在第二绝缘体层上形成顶部阻挡中间层 并且在顶部阻挡中间层上形成接触层。
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公开(公告)号：US08031528B2
公开(公告)日：2011-10-04
申请号：US12557721
申请日：2009-09-11
Applicant: Ashot Melik-Martirosian , Ed Runnion , Mark Randolph , Meng Ding
Inventor： Ashot Melik-Martirosian , Ed Runnion , Mark Randolph , Meng Ding
CPC classification number: G11C16/0475 , G11C16/12 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459
Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.
Abstract translation: 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。 在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。
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Patent Agency Ranking
公开(公告)号：US20080083946A1
公开(公告)日：2008-04-10
申请号：US11539984
申请日：2006-10-10
Applicant: Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
Inventor： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
IPC: H01L29/792 , H01L21/8238
CPC classification number: H01L29/792 , H01L21/28273 , H01L27/115 , H01L27/11568
Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.
Abstract translation: 提供了一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，以及缝隙平面天线等离子体氧化用于形成第二绝缘体层的电荷陷阱层。
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17.发明授权Device with ESD protection utilizing a shorting material between electrical pads or leads which are shorted then unshorted by severing the shorting material and then recreating the short by reapplying the shorting material 失效具有ESD保护的装置，利用电焊盘或导线之间的短路材料，短路材料短路，然后通过切断短路材料，然后通过重新应用短路材料重建短路公开(公告)号：US07345853B2
公开(公告)日：2008-03-18
申请号：US11745787
申请日：2007-05-08
Applicant: Meng Ding , Surya Narayan Pattanaik , Chie Ching Poon , Neil Leslie Robertson
Inventor： Meng Ding , Surya Narayan Pattanaik , Chie Ching Poon , Neil Leslie Robertson
IPC: G11B5/39
CPC classification number: G11B5/11 , B23K1/0056 , B23K1/018 , B23K26/0622 , B23K26/354 , B23K2101/42 , G11B5/3906 , G11B5/40
Abstract: A device according to one embodiment includes an electronic component such as an MR sensor, a pair of leads operatively coupled to the electronic component, and shorting material between the leads, the shorting material having been applied by a laser deposition process, the shorting material having been severed. A magnetic storage system according to another embodiment includes magnetic media; and at least one head for reading from and writing to the magnetic media, each head having: a sensor; and a writer coupled to the sensor. The system also includes a pair of pads or leads operatively coupled to the head; shorting material between the leads, the shorting material having been applied by a laser deposition process, the shorting material having been severed; a slider for supporting the head; and a control unit coupled to the head for controlling operation of the head.
Abstract translation: 根据一个实施例的装置包括诸如MR传感器的电子部件，可操作地耦合到电子部件的一对引线以及引线之间的短路材料，通过激光沉积工艺施加了短路材料，所述短路材料具有 被切断 根据另一实施例的磁存储系统包括磁介质; 以及用于从磁介质读取和写入至少一个头部，每个头部具有：传感器; 以及耦合到传感器的写入器。 该系统还包括可操作地耦合到头部的一对垫或引线; 在引线之间短路材料，通过激光沉积工艺施加的短路材料，短路材料已被切断; 用于支撑头部的滑块; 以及耦合到头部用于控制头部的操作的控制单元。
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公开(公告)号：US20080023750A1
公开(公告)日：2008-01-31
申请号：US11461428
申请日：2006-07-31
Applicant: Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
Inventor： Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
IPC: H01L29/788
CPC classification number: H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/513
Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.
Abstract translation: 提供一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，在电荷陷阱层上形成第二绝缘体层，在第二绝缘体层上形成顶部阻挡中间层 并且在顶部阻挡中间层上形成接触层。
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公开(公告)号：US20080012060A1
公开(公告)日：2008-01-17
申请号：US11458046
申请日：2006-07-17
Applicant: Meng Ding , Amol Ramesh Joshi , Lei Xue , Takashi Orimoto , Kuo-Tung Chang
Inventor： Meng Ding , Amol Ramesh Joshi , Lei Xue , Takashi Orimoto , Kuo-Tung Chang
IPC: H01L29/76
CPC classification number: H01L27/11563 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/513 , H01L29/792
Abstract: A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.
Abstract translation: 提供一种存储单元系统，在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，在电荷陷阱层上形成中间层，并与中间层形成第二绝缘体层。
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公开(公告)号：US07199986B2
公开(公告)日：2007-04-03
申请号：US10782301
申请日：2004-02-18
Applicant: Marie-Claire Cyrille , Meng Ding , Kuok-San Ho , Prakash Kasiraj , Ernesto Marinero , James Lamar Nix , Brian York
Inventor： Marie-Claire Cyrille , Meng Ding , Kuok-San Ho , Prakash Kasiraj , Ernesto Marinero , James Lamar Nix , Brian York
IPC: G11B5/33
CPC classification number: G11B5/3932
Abstract: A magnetic sensor is provided, having two bias layers separated by a decoupling layer to eliminate exchange coupling between the bias layers. The two bias layers may have differing coercivities, such that the biases provided by the bias layers to the free layer are independently adjustable. The grain structures of the two bias layers may be substantially decorrelated by the decoupling layer.
Abstract translation: 提供了一种磁传感器，其具有由解耦层隔开的两个偏置层，以消除偏置层之间的交换耦合。 两个偏置层可以具有不同的矫顽力，使得由偏置层提供给自由层的偏压是独立可调的。 两个偏置层的晶粒结构可以通过去耦层基本上去相关。
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