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    Fabrication of MEMS devices with spin-on glass
    11.
    发明申请
    Fabrication of MEMS devices with spin-on glass 有权
    用旋涂玻璃制造MEMS器件

    公开(公告)号：US20050145962A1

    公开(公告)日：2005-07-07

    申请号：US11054946

    申请日：2005-02-11

    申请人： Luc Ouellet

    发明人： Luc Ouellet

    IPC分类号： B81C1/00 ,  G03F7/09 ,  H01L21/3213 ,  H01L21/00 ,  H01L27/14 ,  H01L29/82

    CPC分类号： B81C1/00619 ,  G03F7/094 ,  H01L21/32137 ,  H01L21/32139 ,  Y10T428/24479

    摘要： A method of making an etched structure in the fabrication of a MEMS device involves depositing a bulk layer, typically of polysilicon, prone to surface roughness. At least one layer of photo-insensitive spin-on planarizing material, such as silicate-based spin-on glass, is formed on the bulk layer to reduce surface roughness. This is patterned with a photoresist layer. A deep etch is then performed through the photoresist layer into the bulk layer. This technique results in much more precise etch structures.

    摘要翻译： 在MEMS器件的制造中制造蚀刻结构的方法包括沉积容易产生表面粗糙度的通常为多晶硅的体层。 在本体层上形成至少一层光不敏感的旋涂平面化材料，例如基于硅酸盐的旋涂玻璃，以降低表面粗糙度。 用光致抗蚀剂层图案化。 然后通过光致抗蚀剂层进行深刻蚀到体层中。 这种技术导致更精确的蚀刻结构。

    Method of preventing cracking in optical quality silica layers
    13.
    发明授权
    Method of preventing cracking in optical quality silica layers 失效
    防止光学质量二氧化硅层破裂的方法

    公开(公告)号：US06749893B2

    公开(公告)日：2004-06-15

    申请号：US10059117

    申请日：2002-01-31

    申请人： Luc Ouellet ,  Jonathan Lachance ,  Sylvie Archambault

    发明人： Luc Ouellet ,  Jonathan Lachance ,  Sylvie Archambault

    IPC分类号： B05D506

    CPC分类号： G02B6/132 ,  C23C16/402 ,  C23C16/56 ,  G02B2006/12169

    摘要： A method for making an integrated photonic device involves depositing buffer, core and cladding layers on the front side of a wafer. A thick tensile stress layer is deposited on the back side of the wafer just prior to performing a high temperature thermal treatment above 600° C. on the cladding layer to prevent the cracking of the layers as a result of the thermal treatment.

    摘要翻译： 制造集成光子器件的方法包括在晶片的正面上沉积缓冲层，芯层和覆层。 在刚刚在包层之上进行高于600℃的高温热处理之前，在晶片的背面沉积厚的拉伸应力层，以防止由于热处理而导致的层的开裂。

    Method of depositing an optical quality silica film by PECVD
    14.
    发明授权
    Method of depositing an optical quality silica film by PECVD 失效
    通过PECVD沉积光学质量二氧化硅膜的方法

    公开(公告)号：US06716476B2

    公开(公告)日：2004-04-06

    申请号：US09956916

    申请日：2001-09-21

    申请人： Luc Ouellet ,  Jonathan Lachance

    发明人： Luc Ouellet ,  Jonathan Lachance

    IPC分类号： C23C1640

    CPC分类号： C23C16/402 ,  C23C16/56 ,  G02B1/10 ,  G02B6/105 ,  G02B6/132 ,  G02B2006/12169

    摘要： A method is disclosed for depositing an optical quality silica film on a wafer by PECVD. The flows rates for a raw material gas, an oxidation gas, a carrier gas, and a dopant gas are first set at predetermined levels. The total deposition pressure is set at a predetermined level. The deposited film is then subjected to a post deposition heat treatment at a temperature selected to optimize the mechanical properties without affecting the optical properties. Finally, the observed FTIR characteristics of the deposited film are monitored to produce a film having the desired optical and mechanical properties. This technique permits the production of high quality optical films with reduced stress.

    摘要翻译： 公开了一种通过PECVD在晶片上沉积光学质量二氧化硅膜的方法。 首先将原料气体，氧化气体，载气和掺杂剂气体的流量设定为规定量。 总沉积压力设定在预定水平。 然后将沉积的膜在选定的温度下进行后沉积热处理，以优化机械性能而不影响光学性能。 最后，监测沉积膜的观察到的FTIR特性以产生具有所需光学和机械性能的膜。 该技术允许生产具有降低应力的高质量光学膜。

    Method of protecting light sensitive regions of integrated circuits
    17.
    发明授权
    Method of protecting light sensitive regions of integrated circuits 失效
    保护集成电路光敏区的方法

    公开(公告)号：US6133060A

    公开(公告)日：2000-10-17

    申请号：US10191

    申请日：1998-01-21

    申请人： Ted Darwall ,  Luc Ouellet

    发明人： Ted Darwall ,  Luc Ouellet

    IPC分类号： H01L21/50 ,  H01L23/552 ,  H01L31/0216 ,  H01L21/00

    CPC分类号： H01L31/02164 ,  H01L31/18

    摘要： A semiconductor device includes at least one active region. A thick dielectric film with an opaque layer embedded therein is deposited over the light sensitive active regions to provide protection from incident light without detrimentally affecting the optical properties of an uppermost optically active layer. An active layer is deposited over the thick dielectric film.

    摘要翻译： 半导体器件包括至少一个有源区。 将沉积有不透明层的厚电介质膜沉积在光敏有源区上，以提供对入射光的保护，而不会不利地影响最上面的光学活性层的光学性质。 有源层沉积在厚电介质膜上。

    Stabilization of the interface between tiN and A1 alloys
    18.
    发明授权
    Stabilization of the interface between tiN and A1 alloys 失效
    稳定TiN和A1合金之间的界面

    公开(公告)号：US6127266A

    公开(公告)日：2000-10-03

    申请号：US979956

    申请日：1997-11-26

    申请人： Luc Ouellet ,  Yves Tremblay ,  Luc Gendron

    发明人： Luc Ouellet ,  Yves Tremblay ,  Luc Gendron

    IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/76846 ,  H01L21/76856

    摘要： A method of manufacturing a semiconductor device which includes an interface between a metal layer and a barrier layer of a nitride of a refractory metal, comprising the steps of depositing the barrier layer onto a wafer at high temperature; subjecting the barrier layer to a mixture of oxygen or an oxygen-containing gas and an inert gas in the presence of a plasma at low pressure and for a time sufficient to oxidize the surface of the barrier layer; removing the oxygen-containing gas; and depositing the metal layer onto the oxidized surface without subjecting said wafer to an air break. The method permits high throughput to be achieved at low cost.

    摘要翻译： 一种制造半导体器件的方法，其包括难熔金属的氮化物的金属层和阻挡层之间的界面，包括以下步骤：在高温下将阻挡层沉积在晶片上; 在等离子体存在下，在低压下将阻挡层与氧气或含氧气体和惰性气体的混合物经受足以氧化阻挡层表面的时间; 去除含氧气体; 并且在不对所述晶片进行空气破坏的情况下将金属层沉积到氧化表面上。 该方法允许以低成本实现高产量。

    Integrated processing for an etch module using a hard mask technique
    19.
    发明授权
    Integrated processing for an etch module using a hard mask technique 失效
    使用硬掩模技术的蚀刻模块的集成处理

    公开(公告)号：US6074946A

    公开(公告)日：2000-06-13

    申请号：US794441

    申请日：1997-02-04

    申请人： Luc Ouellet ,  Abdellah Azelmad

    发明人： Luc Ouellet ,  Abdellah Azelmad

    IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/76802 ,  H01L21/31144 ,  Y10S438/942

    摘要： A method of fabricating a semiconductor device includes etching holes through at least one deposited layer to an underlying structure. A hard mask is deposited on an upper surface of a device to be etched, the mask is patterned with the aid of a photoresist, and holes are etched in the hard mask. After removal of the photoresist, contact or via holes are etched through the patterned hard mask in the deposited layer(s) to reach the underlying structure.

    摘要翻译： 制造半导体器件的方法包括通过至少一个沉积层到底层结构的蚀刻孔。 硬掩模沉积在要蚀刻的器件的上表面上，借助于光致抗蚀剂对掩模进行图案化，并且在硬掩模中蚀刻孔。 在去除光致抗蚀剂之后，通过沉积层中的图案化硬掩模蚀刻接触孔或通孔以到达下面的结构。

    Multi-level interconnection CMOS devices with SOG
    20.
    发明授权
    Multi-level interconnection CMOS devices with SOG 失效
    多层互连CMOS器件采用SOG

    公开(公告)号：US5457073A

    公开(公告)日：1995-10-10

    申请号：US39485

    申请日：1993-04-30

    申请人： Luc Ouellet

    发明人： Luc Ouellet

    IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/469

    CPC分类号： H01L21/02337 ,  H01L21/02129 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/316 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/76828 ,  Y10S438/974

    摘要： A method of manufacturing a semiconductor wafer, which includes performing a first metallization to deposit a first layer of interconnect material on a substrate, etching the interconnect material to form interconnect tracks, depositing a first low temperature dielectric layer over the interconnect tracks, planarizing the first low temperature dielectric layer with quasi-inorganic or inorganic spin-on glass by a non-etchback process, depositing a second low temperature dielectric layer over the spin-on glass, etching via holes through the dielectric and spin-on glass layers to reach the tracks of the first interconnect layer, performing an in-situ desorption of physically and chemically bonded water vapour in a dry environment at a temperature of at least 400.degree. C. and not more than 550.degree. C. for a time sufficient to obtain a negligible desorption rate, the temperature exceeding by at least 25.degree. C. the temperature to which the surface of the wafer will be exposed during a subsequent metallization step, and performing the subsequent metallization step to deposit a second interconnect layer extending through the via holes to the first interconnect tracks without re-exposure of the wafer to ambient conditions, and keeping this wafer under vacuum. This technique permits the reliable use of inorganic or quasi-inorganic spin-on glasses in non batch type sputtering equipment.

    摘要翻译： PCT No.PCT / CA91 / 00343 Sec。 371日期：1993年04月30日 102（e）日期1993年4月30日PCT 1991年9月25日PCT公布。 出版物WO92 / 06492 日本时间1992年04月16日。一种制造半导体晶片的方法，包括执行第一金属化以将第一层互连材料沉积在衬底上，蚀刻互连材料以形成互连轨道，沉积第一低温电介质层 互连轨道，通过非回蚀法将准第一低温介电层与准无机或无机旋涂玻璃平坦化，在旋涂玻璃上沉积第二低温电介质层，通过电介质蚀刻通孔和​​旋转 在达到第一互连层的轨道的玻璃层中，在干燥环境中在至少400℃且不高于550℃的温度下进行物理和化学键合的水蒸气的原位解吸，以获得 足以获得可忽略的解吸速率的时间，温度超过至少25℃。晶片表面暴露于的温度 在随后的金属化步骤期间，并且执行随后的金属化步骤以将延伸穿过所述通孔的第二互连层沉积到所述第一互连轨道，而不再将所述晶片暴露于环境条件，并将所述晶片保持在真空状态。 这种技术允许在非批式溅射设备中可靠地使用无机或准无机旋涂眼镜。