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    VERTICAL MEMORY DEVICES
    12.
    发明申请
    VERTICAL MEMORY DEVICES 审中-公开

    公开(公告)号：US20180247950A1

    公开(公告)日：2018-08-30

    申请号：US15801551

    申请日：2017-11-02

    申请人： Su-Ok YUN ,  Jang-Gn YUN ,  Joon-Sung LIM ,  Sung-Min HWANG

    发明人： Su-Ok YUN ,  Jang-Gn YUN ,  Joon-Sung LIM ,  Sung-Min HWANG

    IPC分类号： H01L27/11556 ,  H01L27/11582

    CPC分类号： H01L27/11556 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    摘要： A vertical memory device includes a gate structure on a peripheral circuit region of a substrate, the substrate including a cell region and the peripheral circuit region, and the gate structure including a first gate electrode, second, third, and fourth gate electrodes sequentially disposed at a plurality of levels, respectively, on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a first epitaxial layer extending through the second gate electrode on the cell region of the substrate, a channel extending through the third and fourth gate electrodes in the vertical direction on the first epitaxial layer, and a second epitaxial layer on a portion of the peripheral circuit region of the substrate adjacent the gate structure.

    Three-dimensional semiconductor memory devices
    14.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US09741733B2

    公开(公告)日：2017-08-22

    申请号：US14962263

    申请日：2015-12-08

    申请人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

    发明人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

    IPC分类号： H01L27/115 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573

    CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate. A peripheral transistor and a peripheral interconnection structure may be disposed between the semiconductor substrate and the semiconductor pattern. The peripheral interconnection structure may be electrically connected to the peripheral transistor. Cell gate conductive patterns may be disposed on the semiconductor pattern. The cell vertical structures may extend through the cell gate conductive patterns and may be connected to the semiconductor pattern. Cell bit line contact plugs may be disposed on the cell vertical structures. A bit line may be disposed on the cell bit line contact plugs. A peripheral bit line contact structure may be disposed between the bit line and the peripheral interconnection structure. The peripheral bit line contact structure may extend through the opening of the semiconductor.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    16.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160181101A1

    公开(公告)日：2016-06-23

    申请号：US14963739

    申请日：2015-12-09

    申请人： Jang-gn Yun ,  Joon Sung Lim ,  Jae-ho Ahn

    发明人： Jang-gn Yun ,  Joon Sung Lim ,  Jae-ho Ahn

    IPC分类号： H01L21/033 ,  H01L27/115 ,  H01L29/06

    CPC分类号： H01L27/11565 ,  H01L21/0337 ,  H01L21/3086 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/0653

    摘要： A semiconductor device includes a plurality of line patterns including at least two continuous line repetition units having, as one of the line repetition unit, four line patterns continuously arranged in a first direction and having variable widths based on location. To form the plurality of line patterns including the at least two continuous line repetition units, a plurality of reference patterns are formed repeatedly at a uniform reference pitch on a feature layer. A plurality of first spacers covering both side walls of each of the plurality of reference patterns are formed. A plurality of second spacers covering both side walls of each of the plurality of first spacers are formed by removing the plurality of reference patterns. The feature layer is etched using the plurality of second spacers as an etch mask by removing the plurality of first spacers.

    摘要翻译： 一种半导体器件包括至少两条连续线重复单元的多个线图案，所述至少两条连续线重复单元具有作为行重复单元之一的四条线图案，其以第一方向连续排列并且基于位置具有可变宽度。 为了形成包括至少两个连续线重复单元的多个线条图案，在特征层上以均匀的参考间距重复地形成多个参考图案。 形成多个第一间隔件，其覆盖多个基准图案中的每一个的两个侧壁。 通过去除多个参考图案来形成覆盖多个第一间隔物中每一个的两个侧壁的多个第二间隔件。 使用多个第二间隔物作为蚀刻掩模来蚀刻特征层，通过去除多个第一间隔物。

    SEMICONDUCTOR DEVICES
    17.
    发明申请
    SEMICONDUCTOR DEVICES 有权
    半导体器件

    公开(公告)号：US20160163732A1

    公开(公告)日：2016-06-09

    申请号：US14962263

    申请日：2015-12-08

    申请人： Joon-Sung LIM ,  Jang-Gn YUN ,  Jaesun YUN

    发明人： Joon-Sung LIM ,  Jang-Gn YUN ,  Jaesun YUN

    IPC分类号： H01L27/115 ,  H01L23/522 ,  H01L23/528

    CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate. A peripheral transistor and a peripheral interconnection structure may be disposed between the semiconductor substrate and the semiconductor pattern. The peripheral interconnection structure may be electrically connected to the peripheral transistor. Cell gate conductive patterns may be disposed on the semiconductor pattern. The cell vertical structures may extend through the cell gate conductive patterns and may be connected to the semiconductor pattern. Cell bit line contact plugs may be disposed on the cell vertical structures. A bit line may be disposed on the cell bit line contact plugs. A peripheral bit line contact structure may be disposed between the bit line and the peripheral interconnection structure. The peripheral bit line contact structure may extend through the opening of the semiconductor.

    摘要翻译： 提供了制造半导体器件的半导体器件和方法。 半导体器件可以包括在半导体衬底上包括开口的半导体图案。 外围晶体管和外围互连结构可以设置在半导体衬底和半导体图案之间。 外围互连结构可以电连接到外围晶体管。 单元栅极导电图案可以设置在半导体图案上。 单元垂直结构可以延伸穿过单元栅极导电图案并且可以连接到半导体图案。 单元位线接触插头可以设置在单元垂直结构上。 位线可以设置在单元位线接触插头上。 外围位线接触结构可以设置在位线和外围互连结构之间。 外围位线接触结构可延伸穿过半导体的开口。

    Semiconductor devices and methods of fabricating the same
    18.
    发明授权
    Semiconductor devices and methods of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08288228B2

    公开(公告)日：2012-10-16

    申请号：US13032286

    申请日：2011-02-22

    申请人： Joon-Sung Lim ,  Jongho Park ,  Okcheon Hong ,  Jung-Hwan Park

    发明人： Joon-Sung Lim ,  Jongho Park ,  Okcheon Hong ,  Jung-Hwan Park

    IPC分类号： H01L21/8247

    CPC分类号： H01L27/11529 ,  H01L27/11526 ,  H01L27/11573 ,  H01L28/20

    摘要： Semiconductor devices and a methods of fabricating the semiconductor devices are provided. The methods may include forming a pattern on a substrate, forming a capping dielectric layer on the pattern, and thermally processing the substrate. After thermally processing the substrate, the methods may further include forming a diffusion barrier layer by a nitride process that may include supplying nitrogen to the capping dielectric layer. The methods may also include forming an etching stop layer on the diffusion barrier layer, forming an inter-layer dielectric layer on the etching stop layer, and planarizing the inter-layer dielectric layer.

    摘要翻译： 提供半导体器件和制造半导体器件的方法。 所述方法可以包括在衬底上形成图案，在图案上形成覆盖电介质层，并热处理衬底。 在热处理衬底之后，所述方法还可以包括通过氮化工艺形成扩散阻挡层，所述氮化工艺可以包括向覆盖电介质层供应氮。 所述方法还可以包括在扩散阻挡层上形成蚀刻停止层，在蚀刻停止层上形成层间电介质层，并平坦化层间电介质层。

    SEMICONDUCTOR MEMORY DEVICE INCLUDING DOUBLE SPACERS ON SIDEWALL OF FLATING GATE, ELECTRONIC DEVICE INCLUDING THE SAME
    19.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING DOUBLE SPACERS ON SIDEWALL OF FLATING GATE, ELECTRONIC DEVICE INCLUDING THE SAME 有权
    半导体存储器件，其中包括在平板门，包括它们的电子器件上的双重间隔

    公开(公告)号：US20090096005A1

    公开(公告)日：2009-04-16

    申请号：US12133587

    申请日：2008-06-05

    申请人： Joon-Sung LIM ,  Jong-Ho PARK ,  Hyun-Chul BACK ,  Sung-Hun LEE

    发明人： Joon-Sung LIM ,  Jong-Ho PARK ,  Hyun-Chul BACK ,  Sung-Hun LEE

    IPC分类号： H01L27/088

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    摘要： A semiconductor memory device includes a device isolation layer formed in a semiconductor substrate to define a plurality of active regions. Floating gates are disposed on the active regions. A control gate line overlaps top surfaces of the floating gates and crosses over the active regions. The control gate line has an extending portion disposed in a gap between adjacent floating gates and overlapping sidewalls of the adjacent floating gates. First spacers are disposed on the sidewalls of the adjacent floating gates. Each of the first spacers extends along a sidewall of the active region and along a sidewall of the device isolation layer. Second spacers are disposed between outer sidewalls of the first spacers and the extending portion and are disposed above the device isolation layer. An electronic device including a semiconductor memory device and a method of fabricating a semiconductor memory device are also disclosed.

    摘要翻译： 半导体存储器件包括形成在半导体衬底中以限定多个有源区的器件隔离层。 浮动门设置在活动区域​​上。 控制栅极线与浮动栅极的顶表面重叠，并在有源区域上交叉。 控制栅极线具有设置在相邻浮动栅极之间的间隙中的延伸部分和相邻浮动栅极的重叠侧壁之间。 第一间隔件设置在相邻浮动门的侧壁上。 每个第一间隔件沿着有源区的侧壁并且沿着器件隔离层的侧壁延伸。 第二间隔件设置在第一间隔件的外侧壁和延伸部分之间，并且设置在装置隔离层的上方。 还公开了一种包括半导体存储器件和制造半导体存储器件的方法的电子器件。

    Three-dimensional semiconductor memory devices
    20.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US10038009B2

    公开(公告)日：2018-07-31

    申请号：US15662714

    申请日：2017-07-28

    申请人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

    发明人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

    IPC分类号： H01L27/115 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11573

    CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor.