公开(公告)号：US08921977B2

公开(公告)日：2014-12-30

申请号：US13333564

申请日：2011-12-21

Applicant: Jen Jui Huang ,  Che Chi Lee ,  Shih Shu Tsai ,  Cheng Shun Chen ,  Shao Ta Hsu ,  Chao Wen Lay ,  Chun I Hsieh ,  Ching Kai Lin

Inventor： Jen Jui Huang ,  Che Chi Lee ,  Shih Shu Tsai ,  Cheng Shun Chen ,  Shao Ta Hsu ,  Chao Wen Lay ,  Chun I Hsieh ,  Ching Kai Lin

IPC: H01L29/92 ,  H01L27/108 ,  H01L27/105

CPC classification number: H01L27/10817 ,  H01L27/105 ,  H01L27/10852 ,  H01L28/91

Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.

Abstract translation: 电容器阵列包括多个电容器和支撑框架。 每个电容器包括电极。 支撑框架支撑多个电极，并且包括对应于多个电极的多个支撑结构。 每个支撑结构可以围绕相应的电极。 支撑框架可以包括掺杂可氧化材料的氧化物。

公开(公告)号：US07915133B2

公开(公告)日：2011-03-29

申请号：US11953481

申请日：2007-12-10

Applicant: Kuo-Yao Cho ,  Wen-Bin Wu ,  Chiang-Lin Shih ,  Jen-Jui Huang

Inventor： Kuo-Yao Cho ,  Wen-Bin Wu ,  Chiang-Lin Shih ,  Jen-Jui Huang

IPC: H01L21/20

CPC classification number: H01L29/945 ,  H01L29/66181

Abstract: A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the substrate; the ring-type trench including an inner wall and an outer wall; and forming a capacitor structure on the inner wall and the outer wall of the ring-type trench.

Abstract translation: 提供一种形成环型电容器的方法。 该方法包括提供基板; 在所述衬底上形成图案化掩模层，所述图案化掩模层限定环形图案; 通过使用图案化掩模层作为掩模去除衬底，以在衬底中形成环型沟槽; 所述环形沟槽包括内壁和外壁; 并在环形沟槽的内壁和外壁上形成电容器结构。

公开(公告)号：US07799512B2

公开(公告)日：2010-09-21

申请号：US11742272

申请日：2007-04-30

Applicant: Kuo-Yao Cho ,  Jen-Jui Huang

Inventor： Kuo-Yao Cho ,  Jen-Jui Huang

IPC: G03F7/26

CPC classification number: H01L21/31144 ,  H01L21/0337

Abstract: A method for forming a ring pattern is disclosed. The ring pattern has a first wall and a second wall. The method includes the following steps: (a) providing a substrate; (b) forming a dielectric layer on the substrate; (c) forming a first patterned photoresist layer on the dielectric layer, the first patterned photoresist layer defining the first wall; (d) etching the dielectric layer to a predetermined depth by using the first patterned photoresist as a mask, and then removing the first patterned photoresist layer; (e) forming a second patterned photoresist layer on the dielectric layer, the second patterned photoresist layer defining the second wall; (f) etching the dielectric layer by using the second patterned photoresist layer as a mask so as to form the ring pattern having the first wall and the second wall.

Abstract translation: 公开了一种形成环形图案的方法。 环形图案具有第一壁和第二壁。 该方法包括以下步骤：（a）提供衬底; （b）在基板上形成电介质层; （c）在所述电介质层上形成第一图案化光致抗蚀剂层，所述第一图案化光刻胶层限定所述第一壁; （d）通过使用第一图案化的光致抗蚀剂作为掩模将电介质层蚀刻到预定的深度，然后去除第一图案化的光致抗蚀剂层; （e）在所述电介质层上形成第二图案化光致抗蚀剂层，所述第二图案化光致抗蚀剂层限定所述第二壁; （f）通过使用第二图案化光致抗蚀剂层作为掩模蚀刻介电层，以便形成具有第一壁和第二壁的环形图案。

公开(公告)号：US20100097854A1

公开(公告)日：2010-04-22

申请号：US12352588

申请日：2009-01-12

Applicant: Jen-Jui Huang ,  Hung-Ming Tsai ,  Kuo-Chung Chen

Inventor： Jen-Jui Huang ,  Hung-Ming Tsai ,  Kuo-Chung Chen

IPC: G11C16/04 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L27/11521 ,  G11C16/3427 ,  H01L29/40114 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

Abstract: A flash memory including a substrate having a recess, a buried bit line, a word line, a single side insulating layer, a floating gate, a tunneling dielectric layer, a control gate, and an inter-gate dielectric layer is provided. The buried bit line extends below the recess of the substrate along a first direction. The word line is on the substrate, and extends above the recess along a second direction. The single side insulating layer is on a first sidewall of the recess. The floating gate is on a second sidewall of the recess to be opposite to the single side insulating layer. The tunneling dielectric layer is sandwiched by the floating gate and the substrate to contact the buried bit line. The control gate fills the recess and contacts the word line. The inter-gate dielectric layer is sandwiched by the control gate and the floating gate.

Abstract translation: 提供一种闪速存储器，其包括具有凹部，掩埋位线，字线，单侧绝缘层，浮动栅极，隧道电介质层，控制栅极和栅极间介电层的衬底。 埋置的位线沿着第一方向延伸到衬底的凹部下方。 字线在基板上，并且沿着第二方向在凹部上方延伸。 单侧绝缘层位于凹部的第一侧壁上。 浮动栅极位于凹槽的与单侧绝缘层相对的第二侧壁上。 隧道电介质层被浮动栅极和衬底夹在接触掩埋位线之间。 控制门填充凹槽并接触字线。 栅极间电介质层被控制栅极和浮动栅极夹在中间。

公开(公告)号：US20080286934A1

公开(公告)日：2008-11-20

申请号：US11953481

申请日：2007-12-10

Applicant: Kuo-Yao CHO ,  Wen-Bin WU ,  Chiang-Lin SHIH ,  Jen-Jui HUANG

Inventor： Kuo-Yao CHO ,  Wen-Bin WU ,  Chiang-Lin SHIH ,  Jen-Jui HUANG

IPC: H01L21/02

CPC classification number: H01L29/945 ,  H01L29/66181

Abstract: A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the substrate; the ring-type trench including an inner wall and an outer wall; and forming a capacitor structure on the inner wall and the outer wall of the ring-type trench.

Abstract translation: 提供一种形成环型电容器的方法。 该方法包括提供基板; 在所述衬底上形成图案化掩模层，所述图案化掩模层限定环形图案; 通过使用图案化掩模层作为掩模去除衬底，以在衬底中形成环型沟槽; 所述环形沟槽包括内壁和外壁; 并在环形沟槽的内壁和外壁上形成电容器结构。

公开(公告)号：US08921183B2

公开(公告)日：2014-12-30

申请号：US12962655

申请日：2010-12-08

Applicant: Jen-Jui Huang ,  Hung-Ming Tsai

Inventor： Jen-Jui Huang ,  Hung-Ming Tsai

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76227

Abstract: A method for fabricating a trench isolation structure is described. A trench is formed in a substrate. A liner layer is formed at least in the trench. A precursor layer is formed at least on the sidewalls of the trench. The precursor layer is converted to an insulating layer that has a larger volume than the precursor layer and fills up the trench.

Abstract translation: 描述了一种用于制造沟槽隔离结构的方法。 在衬底中形成沟槽。 至少在沟槽中形成衬垫层。 至少在沟槽的侧壁上形成前体层。 前体层被转换成具有比前体层更大的体积并填充沟槽的绝缘层。

公开(公告)号：US20140070359A1

公开(公告)日：2014-03-13

申请号：US13615526

申请日：2012-09-13

Applicant: Shian-Jyh Lin ,  Jeng-Ping Lin ,  Chin-Piao Chang ,  Jen-Jui Huang

Inventor： Shian-Jyh Lin ,  Jeng-Ping Lin ,  Chin-Piao Chang ,  Jen-Jui Huang

IPC: H01L27/00

CPC classification number: H01L21/3081 ,  H01L21/76224

Abstract: A memory array includes a rhomboid-shaped AA region surrounded by a first and second STI structures. The first STI structure extends along a first direction on the longer sides of the rhomboid-shaped AA region and has a depth d1. The second STI structure extends along the second direction on the shorter sides of the rhomboid-shaped AA region and has two depths: d2 and d3, wherein d1 and d2 are shallower than d3.

Abstract translation: 存储器阵列包括由第一和第二STI结构围绕的菱形形状的AA区域。 第一STI结构在菱形AA区域的长边上沿着第一方向延伸并且具有深度d1。 第二STI结构沿着菱形AA区域的较短边沿第二方向延伸，并且具有两个深度：d2和d3，其中d1和d2比d3浅。

公开(公告)号：US20140036565A1

公开(公告)日：2014-02-06

申请号：US13565289

申请日：2012-08-02

Applicant: Shian Jyh LIN ,  Jen Jui Huang

Inventor： Shian Jyh LIN ,  Jen Jui Huang

IPC: H01L21/768 ,  G11C5/06

CPC classification number: H01L27/1052 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/10891

Abstract: An exemplary memory device includes a substrate and two word lines extending on the substrate. The substrate includes an active area. The two word lines are formed on the active area. Each word line includes a recessed portion corresponding to the active area. The recessed portion is defined by a planar top surface.

Abstract translation: 示例性存储器件包括衬底和在衬底上延伸的两个字线。 基板包括有源区。 两个字线形成在有源区上。 每个字线包括对应于有效区域的凹部。 凹部由平坦的顶面限定。

公开(公告)号：US20100032743A1

公开(公告)日：2010-02-11

申请号：US12236487

申请日：2008-09-23

Applicant: Jen-Jui Huang ,  Hung-Ming Tsai ,  Kuo-Chung Chen

Inventor： Jen-Jui Huang ,  Hung-Ming Tsai ,  Kuo-Chung Chen

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

Abstract: A dynamic random access memory (DRAM) structure has a stacked capacitor disposed above an upper source/drain region of a vertical transistor having a surrounding gate. The gates of each row of a memory array are electrically connected with a buried word line. Each of bit lines is disposed between two adjacent columns of transistors and electrically connected with lower source/drain regions through bit line contacts. The DRAM structure may have a unit cell size of 4F2.

Abstract translation: 动态随机存取存储器（DRAM）结构具有堆叠电容器，其设置在具有周围栅极的垂直晶体管的上部源极/漏极区域之上。 存储器阵列的每行的栅极与掩埋字线电连接。 每个位线设置在两个相邻的晶体管列之间，并通过位线触点与下部源极/漏极区电连接。 DRAM结构可以具有4F2的单元电池尺寸。

公开(公告)号：US20080268640A1

公开(公告)日：2008-10-30

申请号：US11780484

申请日：2007-07-20

Applicant: Yu-Chung Fang ,  Hong-Wen Lee ,  Kuo-Chung Chen ,  Jen-Jui Huang ,  Jing-Kae Liou

Inventor： Yu-Chung Fang ,  Hong-Wen Lee ,  Kuo-Chung Chen ,  Jen-Jui Huang ,  Jing-Kae Liou

IPC: H01L21/441 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76895 ,  H01L27/10888

Abstract: A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer.

Abstract translation: 一种用于形成位线接触插塞的方法包括：提供包括晶体管的衬底，所述晶体管在栅极结构的两侧包括栅极结构和源极/漏极; 形成导电层，位线接触材料层和硬掩模层; 执行使用导电层作为蚀刻停止层的蚀刻工艺，以蚀刻位线接触材料层和硬掩模层，并在源极/漏极上形成位线接触插塞。 晶体管结构包括在栅极结构的两侧处的栅极结构和源极/漏极，覆盖栅极结构的一部分并连接到源极/漏极的导电层，以及布置在导电层上的位线接触插塞， 直接连接到导电层。