公开(公告)号：US06477098B1

公开(公告)日：2002-11-05

申请号：US08994906

申请日：1997-12-19

申请人： George B. Raad

发明人： George B. Raad

IPC分类号： G11C702

CPC分类号： G11C7/18 ,  G11C11/4097

摘要： A memory-cell array includes several memory cells arranged in rows and columns. The memory cells in each row include an access terminal coupled to an associated word line. The memory cells in each column are coupled between a respective first digit line and a respective complementary digit line. The complementary digit line is divided into several portions. A sense amplifier has first and second data terminals with the first data terminal coupled to the first digit line. The memory-cell array includes several first isolation devices, each first isolation device selectively coupling an associated portion of the complementary digit line to the second data terminal of the sense amplifier.

摘要翻译： 存储单元阵列包括以行和列排列的多个存储单元。 每行中的存储单元包括耦合到相关字线的接入终端。 每列中的存储器单元耦合在相应的第一数字线和相应的互补数字线之间。 互补数字线分为几个部分。 读出放大器具有第一和第二数据端，第一数据端耦合到第一数字线。 存储单元阵列包括几个第一隔离器件，每个第一隔离器件选择性地将互补数字线的相关部分耦合到读出放大器的第二数据端。

公开(公告)号：US06445610B1

公开(公告)日：2002-09-03

申请号：US09929611

申请日：2001-08-14

申请人： Stephen R. Porter ,  George B. Raad ,  Stephen L. Casper

发明人： Stephen R. Porter ,  George B. Raad ,  Stephen L. Casper

IPC分类号： G11C1124

CPC分类号： G11C7/06 ,  G11C11/4091

摘要： A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage pumped higher than the supply voltage during read time to ensure that a small differential voltage on the digit lines is correctly read. A lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time. During restore time, the isolation gate voltage is again raised above the operating voltage to minimize the effects of isolation transistor threshold voltage, Vt. In further embodiments, the higher voltage is only provided during restore time and the read and sense voltages are varied between the higher and lower voltage.

摘要翻译： 在包含许多存储单元的数字线和读出放大器之间的DRAM器件中的隔离晶体管的栅极提供可变电压。 隔离晶体管的栅极被提供为在读取时间期间高于电源电压的电压，以确保数字线上的小差分电压被正确读取。 在感测时间提供较低的电压，使得隔离门在感测时间期间提供更高的电阻。 在恢复时间期间，隔离栅极电压再次升高到高于工作电压，以最小化隔离晶体管阈值电压Vt的影响。在另外的实施例中，仅在恢复时间期间提供较高电压，并且读取和检测电压在 更高和更低的电压。

公开(公告)号：US6104652A

公开(公告)日：2000-08-15

申请号：US389106

申请日：1999-09-02

申请人： George B. Raad ,  Stephen L. Casper

发明人： George B. Raad ,  Stephen L. Casper

IPC分类号： G11C7/00 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4094

CPC分类号： G11C11/4094 ,  G11C11/4074 ,  G11C11/4091

摘要： A memory device that uses a dynamic cell plate sensing scheme. The memory device includes an array of word lines and complementary bit line/plate line pairs. A number of memory cells are located at the intersection of selected word lines and bit line/plate line pairs. A sense amplifier is coupled to the complementary bit line/plate line pairs. The memory device also includes an equilibrate circuit that ac equilibrates a complementary bit line/plate line pair at an equilibration voltage between high and low logic levels prior to reading data. The equilibration voltage and the high and low logic levels for the memory cell are chosen such that a fluctuation in the voltage on one of the plate lines does not corrupt data stored in unaccessed memory cells coupled to the same plate line.

摘要翻译： 一种使用动态单元板感测方案的存储器件。 存储器件包括字线阵列和互补的位线/板线对。 多个存储单元位于选定字线和位线/板线对的交点处。 读出放大器耦合到互补位线/板线对。 存储器件还包括平衡电路，其在读取数据之前在平衡电压之间平衡互补的位线/板线对在高逻辑电平和低逻辑电平之间。 选择存储器单元的平衡电压和高和低逻辑电平，使得一个板线上的电压的波动不会损坏存储在耦合到同一板线的未处理的存储器单元中的数据。

公开(公告)号：US5905686A

公开(公告)日：1999-05-18

申请号：US10730

申请日：1998-01-22

申请人： George B. Raad

发明人： George B. Raad

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C7/00

CPC分类号： G11C7/065 ,  G11C11/4091

摘要： A sense amplifier senses a small voltage differential across true and complementary digit lines in a dynamic random access memory (DRAM) integrated circuit. The sensed voltage is further separated and amplified into full logic levels. Activating the P-sense amplifier before the N-sense amplifier speeds sensing. The P-sense amplifier control signal is capacitively coupled to each of the true and complementary digit lines. The P-sense amplifier further increases the more positive digit line to the power supply voltage V.sub.cc. The other digit line is at a voltage more positive than its equilibration voltage, speeding conduction of a subsequently activated N-sense amplifier, particularly for low values of V.sub.cc, in which the threshold voltages of the NFETs in the N-sense amplifier are close to the equilibration voltage. Capacitor elements need not be added to the sense amplifier layout.

摘要翻译： 感测放大器感测动态随机存取存储器（DRAM）集成电路中真实和互补数字线路上的小电压差。 感测电压进一步分离并放大到完全逻辑电平。 在N检测放大器加速检测之前激活P读出放大器。 P读出放大器控制信号电容耦合到每个真实和互补的数字线。 P读出放大器进一步增加了更多的正数字线到电源电压Vcc。 另一个数字线的电压比其平衡电压更正，电压随后激活的N检波放大器，尤其是对于低Vcc值，其中N型放大器中的NFET的阈值电压接近 平衡电压。 电容元件不需要添加到读出放大器布局。

公开(公告)号：US5898635A

公开(公告)日：1999-04-27

申请号：US63418

申请日：1998-04-20

申请人： George B. Raad ,  Stephen L. Casper

发明人： George B. Raad ,  Stephen L. Casper

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C5/143

摘要： A power-up circuit in a computer system drives a memory device such as a dynamic random access memory (DRAM) to an initial condition after the computer system is turned on or reset. The power-up circuit also advantageously drives the memory device into the initial condition upon detecting a transient such as a negative glitch in a supply voltage being provided to the memory device. The power-up circuit includes a voltage level detector which causes a power-up signal to be provided to the memory device upon detecting that the supply voltage is less than a threshold voltage of the memory device which is necessary for the memory device to operate in an operational state. The power-up circuit also includes a delay circuit which causes the power-up signal to be provided to the memory device upon detecting that the supply voltage is beginning to rise from a quiescent voltage and at least until an amount of time determined by an RC time constant of the memory device for the memory device to enter the initial condition has passed. In response to receiving the power-up signal, the memory device enters the initial condition.

摘要翻译： 计算机系统中的上电电路在计算机系统接通或复位之后将诸如动态随机存取存储器（DRAM）的存储器件驱动到初始状态。 在检测到诸如提供给存储器件的电源电压中的负毛刺之类的瞬态时，上电电路还有利地将存储器件驱动到初始状态。 上电电路包括电压电平检测器，其在检测到电源电压小于存储器件在操作中所需的存储器件的阈值电压时，将上电信号提供给存储器件 操作状态。 上电电路还包括延迟电路，其在检测到电源电压从静态电压开始上升时使得上电信号被提供给存储器件，并且至少直到由RC确定的时间量 用于存储器件的存储器件的时间常数进入初始条件已经过去了。 响应于接收到上电信号，存储器件进入初始状态。

公开(公告)号：US5768207A

公开(公告)日：1998-06-16

申请号：US706719

申请日：1996-09-06

申请人： George B. Raad ,  Stephen L. Casper

发明人： George B. Raad ,  Stephen L. Casper

IPC分类号： G11C5/14 ,  G11C5/00 ,  G11C7/00

CPC分类号： G11C5/143

摘要： A power-up circuit in a computer system drives a memory device such as a dynamic random access memory (DRAM) to an initial condition after the computer system is turned on or reset. The power-up circuit also advantageously drives the memory device into the initial condition upon detecting a transient such as a negative glitch in a supply voltage being provided to the memory device. The power-up circuit includes a voltage level detector which causes a power-up signal to be provided to the memory device upon detecting that the supply voltage is less than a threshold voltage of the memory device which is necessary for the memory device to operate in an operational state. The power-up circuit also includes a delay circuit which causes the power-up signal to be provided to the memory device upon detecting that the supply voltage is beginning to rise from a quiescent voltage and at least until an amount of time determined by an RC time constant of the memory device for the memory device to enter the initial condition has passed. In response to receiving the power-up signal, the memory device enters the initial condition.

公开(公告)号：US07669068B2

公开(公告)日：2010-02-23

申请号：US11449499

申请日：2006-06-07

申请人： George B. Raad

发明人： George B. Raad

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F13/28

CPC分类号： G06F1/3237 ,  G06F1/04 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G11C7/20 ,  G11C7/22 ,  G11C7/225 ,  G11C2207/2227 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention may be used to reduce power consumption by reducing operating current in a memory device. Operating current may be reduced by turning off internal clock drivers that deliver a clock signal during selected periods of time. According to an embodiment of clock control circuitry of the present invention, an internal clock is disabled if a no operation command is detected during periods of time when no read or write burst operation is taking place. Methods, memory devices and computer systems including the clock control circuitry and its functionality are also disclosed.

摘要翻译： 本发明包括用于选择性地关断内部时钟驱动器以减少工作电流的电路，系统和方法。 本发明可以用于通过减少存储器件中的工作电流来降低功耗。 通过关闭在选定的时间段内提供时钟信号的内部时钟驱动器，可以减少工作电流。 根据本发明的时钟控制电路的一个实施例，如果在没有进行读或写脉冲串操作的时段期间检测到无操作命令，则禁止内部时钟。 还公开了包括时钟控制电路及其功能的方法，存储器件和计算机系统。

公开(公告)号：US07277352B2

公开(公告)日：2007-10-02

申请号：US11347162

申请日：2006-02-02

申请人： George B Raad

发明人： George B Raad

IPC分类号： G11C5/14

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.

公开(公告)号：US06684356B2

公开(公告)日：2004-01-27

申请号：US10269623

申请日：2002-10-11

申请人： George B. Raad ,  David L. Pinney

发明人： George B. Raad ,  David L. Pinney

IPC分类号： G11C2900

CPC分类号： G11C29/44 ,  G11C29/34

摘要： A semiconductor memory device is disclosed that can be operated in a speed test mode. The memory device includes an array of memory cells capable of storing data, a control circuit receiving a signal from an external system clock and controlling data transfer operations between the memory device and an external data bus, and a test mode circuit receiving the external clock signal. When operated in speed test mode, the control circuit provides a signal to the test mode circuit enabling its function. A predetermined data pattern is first written to one or more cells, and then subsequently accessed during a read cycle. The enabled test mode circuit compares the contents of an internal data bus to the predetermined data pattern at a time referenced to the system clock signal. In the case of a failed comparison, the test mode circuit produces a signal that places the external data bus in a high impedance state. The disclosed memory device is therefore capable of itself providing some of the test functions previously provided by external testing equipment, and speed testing equipment in particular.

摘要翻译： 公开了可以以速度测试模式操作的半导体存储器件。 存储器件包括能够存储数据的存储器单元阵列，接收来自外部系统时钟的信号的控制电路以及控制存储器件与外部数据总线之间的数据传输操作，以及接收外部时钟信号的测试模式电路 。 当在速度测试模式下运行时，控制电路向测试模式电路提供信号，使其能够工作。 首先将预定数据模式写入一个或多个单元，然后在读周期期间随后访问。 使能的测试模式电路在参考系统时钟信号的时间将内部数据总线的内容与预定数据模式进行比较。 在失败的比较情况下，测试模式电路产生使外部数据总线处于高阻抗状态的信号。 因此，所公开的存储器件本身能够提供先前由外部测试设备，特别是速度测试设备提供的一些测试功能。

公开(公告)号：US06356492B1

公开(公告)日：2002-03-12

申请号：US09639991

申请日：2000-08-16

申请人： George B. Raad

发明人： George B. Raad

IPC分类号： G11C700

CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C11/4074

摘要： A latch circuit provides an equilibration voltage to a plurality of equilibrate circuits in a memory device. If a row to column short occurs which draws too much current from the latch circuit, the latch circuit will change states and cease supplying a voltage to the equilibrate circuit, thereby limiting current drain on the memory device.

摘要翻译： 锁存电路为存储器件中的多个平衡电路提供平衡电压。 如果从锁存电路吸收太多的电流，则发生行到列的短路，锁存电路将改变状态并停止向平衡电路提供电压，从而限制存储器件上的电流消耗。