公开(公告)号：US07142446B2

公开(公告)日：2006-11-28

申请号：US10902728

申请日：2004-07-29

申请人： Scott J. Derner ,  Stephen R. Porter ,  Scot M. Graham ,  Ethan A. Williford ,  Kevin G. Duesman

发明人： Scott J. Derner ,  Stephen R. Porter ,  Scot M. Graham ,  Ethan A. Williford ,  Kevin G. Duesman

IPC分类号： G11C11/24

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/1048 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/002

摘要： A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.

公开(公告)号：US07091067B2

公开(公告)日：2006-08-15

申请号：US10930511

申请日：2004-08-31

申请人： Stephen R. Porter ,  Scott J. Derner

发明人： Stephen R. Porter ,  Scott J. Derner

IPC分类号： H01L21/82

CPC分类号： H01L23/5252 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method and apparatus are disclosed for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.

摘要翻译： 公开了通过轻度掺杂电连接区域来调节反熔丝编程电流的方法和装置，使得区域的电阻以非线性方式响应于电压变化。 以这种方式，可以产生可变电阻器或可变电阻晶体管，其响应于施加的电压而改变其电阻，并且因此可限制编程电流，而不限制对串行连接的反熔丝的较小的读取电流。

公开(公告)号：US06816425B2

公开(公告)日：2004-11-09

申请号：US10775231

申请日：2004-02-11

申请人： Scot M. Graham ,  Scott J. Derner ,  Stephen R. Porter

发明人： Scot M. Graham ,  Scott J. Derner ,  Stephen R. Porter

IPC分类号： G11C700

CPC分类号： G11C7/06 ,  G11C11/4091

摘要： A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.

公开(公告)号：US06787400B2

公开(公告)日：2004-09-07

申请号：US10346668

申请日：2003-01-16

申请人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

发明人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

IPC分类号： H01L21332

CPC分类号： H01L27/0266 ,  H01L27/0255 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electrostatic discharge protection device is formed in a substrate and contains a drain area of a first dopant concentration abutting an extended drain area having a dopant concentration lower than the first dopant concentration. Similarly, a highly doped source area abuts a lower doped source extension area. The source and drain are laterally bounded by oxide regions and covered by an insulation layer. The areas of lower doping prevent charge crowding during an electrostatic discharge event by resistively forcing current though the nearly planer bottom surface of the drain, rather than the curved drain extension. In addition, a highly doped buried layer can abut an area of a graded doping level. By adjusting the doping levels of the graded areas and the buried layers, the substrate breakdown voltage is pre-selected.

摘要翻译： 静电放电保护器件形成在衬底中，并且包含与掺杂剂浓度低于第一掺杂剂浓度的延伸漏极区相邻的第一掺杂剂浓度的漏区。 类似地，高掺杂源极区域邻接下掺杂源极延伸区域。 源极和漏极由氧化物区域横向界定并被绝缘层覆盖。 较低掺杂的区域通过在漏极的几乎平的底部表面电阻强制电流而不是弯曲的漏极延伸来防止静电放电事件期间的电荷拥挤。 此外，高度掺杂的掩埋层可以邻接渐变掺杂水平的区域。 通过调整分级区域和掩埋层的掺杂水平，预先选择衬底击穿电压。

公开(公告)号：US06628144B2

公开(公告)日：2003-09-30

申请号：US10112380

申请日：2002-03-28

申请人： Daniel R. Loughmiller ,  Stephen R. Porter

发明人： Daniel R. Loughmiller ,  Stephen R. Porter

IPC分类号： H03K1900

CPC分类号： H03K19/1732 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H03K19/1731

摘要： A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including a CMOS multiplexer controlled by a fuse or anti-fuse, an NMOS or PMOS pass gate controlled by a fuse or anti-fuse, or even a fusible link which is severed to effect isolation. Additionally, a circuit is provided that switchably isolates one of two contact pads from a logic circuit.

公开(公告)号：US06593218B2

公开(公告)日：2003-07-15

申请号：US09927275

申请日：2001-08-09

申请人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

发明人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

IPC分类号： H01L21425

CPC分类号： H01L27/0266 ,  H01L27/0255 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electrostatic discharge protection device is formed in a substrate and contains a drain area of a first dopant concentration abutting an extended drain area having a dopant concentration lower than the first dopant concentration. Similarly, a highly doped source area abuts a lower doped source extension area. The source and drain are laterally bounded by oxide regions and covered by an insulation layer. The areas of lower doping prevent charge crowding during an electrostatic discharge event by resistively forcing current though the nearly planer bottom surface of the drain, rather than the curved drain extension. In addition, a highly doped buried layer can abut an area of a graded doping level. By adjusting the doping levels of the graded areas and the buried layers, the substrate breakdown voltage is pre-selected.

公开(公告)号：US06576960B2

公开(公告)日：2003-06-10

申请号：US10095640

申请日：2002-03-11

申请人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

发明人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

IPC分类号： H01L2362

CPC分类号： H01L27/0266 ,  H01L27/0255 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electrostatic discharge protection device is formed in a substrate and contains a drain area of a first dopant concentration abutting an extended drain area having a dopant concentration lower than the first dopant concentration. Similarly, a highly doped source area abuts a lower doped source extension area. The source and drain are laterally bounded by oxide regions and covered by an insulation layer. The areas of lower doping prevent charge crowding during an electrostatic discharge event by resistively forcing current though the nearly planer bottom surface of the drain, rather than the curved drain extension. In addition, a highly doped buried layer can abut an area of a graded doping level. By adjusting the doping levels of the graded areas and the buried layers, the substrate breakdown voltage is pre-selected.

公开(公告)号：US06365937B1

公开(公告)日：2002-04-02

申请号：US09310538

申请日：1999-05-12

申请人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

发明人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

IPC分类号： H01L2362

CPC分类号： H01L27/0266 ,  H01L27/0255 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electrostatic discharge protection device for integrated circuit is formed in a substrate and contains pad contact, rail contact and a deep oxide in a trench in the substrate which isolates pad and rail contacts. The substrate is doped with a first dopant type with a first concentration. A second dopant type in a first inner and a first outer region forms the pad contact; both regions are formed on the substrate. The first inner region is doped higher than the first outer region. Similarly a second dopant type in a second inner and a second outer region forms the rail contact; both regions are formed on the substrate. The second inner region is doped higher than the second outer region. Buried layers are formed of the first dopant type in a second concentration under the pad and rail contacts and under the deep oxide.

摘要翻译： 用于集成电路的静电放电保护装置形成在衬底中，并且在衬底中的沟槽中包含衬垫接触，轨道接触和深氧化物，隔离衬垫和轨道触点。 衬底掺杂有第一浓度的第一掺杂剂类型。 在第一内部和第一外部区域中的第二掺杂剂形式形成焊盘触点; 两个区域形成在基板上。 第一内部区域被掺杂高于第一外部区域。 类似地，在第二内部和第二外部区域中的第二掺杂剂形式形成轨道接触; 两个区域形成在基板上。 第二内部区域被掺杂高于第二外部区域。 掩埋层在第二浓度下由第一掺杂剂形成在焊盘和轨道触点下方以及深氧化物下方。

公开(公告)号：US06297998B1

公开(公告)日：2001-10-02

申请号：US09678979

申请日：2000-10-05

申请人： Scott D. Van de Graaff ,  Stephen R. Porter

发明人： Scott D. Van de Graaff ,  Stephen R. Porter

IPC分类号： G11C700

CPC分类号： G11C7/222 ,  G11C7/1045 ,  G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

摘要： A method and apparatus for testing of semiconductor memory devices. In one embodiment, a test mode of operation is defined for a memory device. In a normal mode of operation, a row line than addressed memory cell is asserted in response to applied external signals corresponding to the beginning of a write-back phase of a read-modify-write cycle. The row line is deasserted on response to applied external signals corresponding to the end of the write-back phase. In the test mode of operation, the row line is asserted in response to the appropriate applied external signals, but deassertion in response to the appropriate applied external signals is suppressed. Instead, deassertion of the row line is forced only upon expiration of a programmable, predetermined time interval following initiation of the write-back phase. The programmable delay can be established by means of an R-C time constant delay circuit. Programmability may be achieved in various ways, including through the provision of metal options selected during the fabrication process, or, alternatively through the provision of laser-actuable fuses or voltage-actuable antifuses. The programmable forced write-back time facilitates reliable comparative testing of multiple parts, and compensates for part-to-part process variations which potentially impact operational performance of different parts to different degrees.

摘要翻译： 一种用于半导体存储器件测试的方法和装置。 在一个实施例中，为存储器件定义了测试操作模式。 在正常操作模式中，响应于对应于读 - 修改 - 写周期的回写阶段的开始的外部信号，断言比寻址存储单元的行行。 响应于对应于回写阶段结束的外部信号，行行被取消置位。 在测试操作模式下，响应于适当的外部信号，行线被断言，但是抑制了对适当的外部信号的响应。 相反，只有在启动回写阶段之后的可编程的预定时间间隔期满时才迫使行线的取消取消。 可以通过R-C时间常数延迟电路建立可编程延迟。 可编程性可以通过各种方式实现，包括通过提供在制造过程期间选择的金属选项，或者通过提供激光可激活的熔丝或电压可启动的反熔丝。 可编程强制回写时间有助于对多个零件进行可靠的比较测试，并补偿部件到零件的过程变化，这些变化会对不同零件的运行性能产生不同程度的影响。

公开(公告)号：US06275409B1

公开(公告)日：2001-08-14

申请号：US09293027

申请日：1999-04-16

申请人： Stephen R. Porter ,  George B. Raad ,  Stephen L. Casper

发明人： Stephen R. Porter ,  George B. Raad ,  Stephen L. Casper

IPC分类号： G11C1124

CPC分类号： G11C7/06 ,  G11C11/4091

摘要： A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage pumped higher than the supply voltage during read time to ensure that a small differential voltage on the digit lines is correctly read. A lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time. During restore time, the isolation gate voltage is again raised above the operating voltage to minimize the effects of isolation transistor threshold voltage, Vt. In further embodiments, the higher voltage is only provided during restore time and the read and sense voltages are varied between the higher and lower voltage.

摘要翻译： 在包含许多存储单元的数字线和读出放大器之间的DRAM器件中的隔离晶体管的栅极提供可变电压。 隔离晶体管的栅极被提供为在读取时间期间高于电源电压的电压，以确保数字线上的小差分电压被正确读取。 在感测时间提供较低的电压，使得隔离门在感测时间期间提供更高的电阻。 在恢复时间期间，隔离栅极电压再次升高到高于工作电压，以最小化隔离晶体管阈值电压Vt的影响。在另外的实施例中，仅在恢复时间期间提供较高电压，并且读取和检测电压在 更高和更低的电压。