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    Apparatus and method to reduce undesirable effects caused by a fault in a memory device
    5.
    发明授权
    Apparatus and method to reduce undesirable effects caused by a fault in a memory device 有权
    用于减少由存储器件中的故障引起的不期望的影响的装置和方法

    公开(公告)号：US07336522B2

    公开(公告)日：2008-02-26

    申请号：US11489119

    申请日：2006-07-19

    申请人： Scott J. Derner ,  Stephen R. Porter ,  Scot M. Graham ,  Ethan A. Williford ,  Kevin G. Duesman

    发明人： Scott J. Derner ,  Stephen R. Porter ,  Scot M. Graham ,  Ethan A. Williford ,  Kevin G. Duesman

    IPC分类号： G11C11/24

    CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/1048 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/002

    摘要： A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.

    摘要翻译： 提供了一种减少存储器件中的电流的方法和装置。 外围设备控制信号被转换为字线关断电压电平，例如负字线电压。 转换后的信号可防止外围设备在字线关闭模式下传导电流，即使发生字线数字短路。 控制信号可以包括列选择装置的列选择信号和用于感测放大器的有源上拉信号等。 此外，为存储器件提供具有高电阻和低电阻分量的均衡电路。 均衡电路限制电流，即使发生字线数字短路。

    Gate voltage testkey for isolation transistor
    8.
    发明授权
    Gate voltage testkey for isolation transistor 失效
    隔离晶体管的栅极电压测试键

    公开(公告)号：US06301172B1

    公开(公告)日：2001-10-09

    申请号：US09794513

    申请日：2001-02-27

    申请人： Scott J. Derner ,  Scot M. Graham

    发明人： Scott J. Derner ,  Scot M. Graham

    IPC分类号： G11C0700

    CPC分类号： G11C29/027 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4078 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5004

    摘要： A semiconductor memory architecture is provided where isolation between adjacent memory cell pairs is accomplished by using an isolation transistor incorporating a programmable gate voltage to minimize subthreshold leakage. A testkey is provided internal to the memory chip that can be enabled while the memory chip is in a test mode. The testkey is capable of testing the isolation transistors for excessive leakage. The testkey is coupled to a translator, responsible for converting control signals from the testkey to isolation gate voltages. The testkey is used to determine whether the isolation transistor is leaky. The translator may adjust the isolation gate voltage to turn the transistors off harder. The present invention may further include an antifuse to permanently change the isolation gate voltage to a suitable value when the semiconductor leaves the testing mode.

    摘要翻译： 提供半导体存储器结构，其中通过使用包含可编程栅极电压的隔离晶体管来实现相邻存储器单元对之间的隔离，以使亚阈值泄漏最小化。 在存储器芯片处于测试模式时，可以在存储器芯片的内部提供测试键，其可以被使能。 测试键能够测试隔离晶体管的过度泄漏。 测试键耦合到转换器，负责将测试键的控制信号转换为隔离栅极电压。 测试键用于确定隔离晶体管是否泄漏。 转换器可以调节隔离栅极电压以使晶体管变得更硬。 本发明还可以包括当半导体离开测试模式时将隔离栅极电压永久地改变到合适值的反熔丝。

    Gate voltage testkey for isolation transistor
    9.
    发明授权
    Gate voltage testkey for isolation transistor 有权
    隔离晶体管的栅极电压测试键

    公开(公告)号：US06556467B2

    公开(公告)日：2003-04-29

    申请号：US09942207

    申请日：2001-08-29

    申请人： Scott J. Derner ,  Scot M. Graham

    发明人： Scott J. Derner ,  Scot M. Graham

    IPC分类号： G11C502

    CPC分类号： G11C29/027 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4078 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5004

    摘要： A semiconductor memory architecture is provided where isolation between adjacent memory cell pairs is accomplished by using an isolation transistor incorporating a programmable gate voltage to minimize subthreshold leakage. A testkey is provided internal to the memory chip that can be enabled while the memory chip is in a test mode. The testkey is capable of testing the isolation transistors for excessive leakage. The testkey is coupled to a translator, responsible for converting control signals from the testkey to isolation gate voltages. The testkey is used to determine whether the isolation transistor is leaky. The translator may adjust the isolation gate voltage to turn the transistors off harder. The present invention may further include an antifuse to permanently change the isolation gate voltage to a suitable value when the semiconductor leaves the testing mode.

    摘要翻译： 提供半导体存储器结构，其中通过使用包含可编程栅极电压的隔离晶体管来实现相邻存储器单元对之间的隔离，以使亚阈值泄漏最小化。 在存储器芯片处于测试模式时，可以在存储器芯片的内部提供测试键，其可以被使能。 测试键能够测试隔离晶体管的过度泄漏。 测试键耦合到转换器，负责将测试键的控制信号转换为隔离栅极电压。 测试键用于确定隔离晶体管是否泄漏。 转换器可以调节隔离栅极电压以使晶体管变得更硬。 本发明还可以包括当半导体离开测试模式时将隔离栅极电压永久地改变到合适值的反熔丝。

    Current limiting antifuse programming path
    10.
    发明授权
    Current limiting antifuse programming path 有权
    限流反熔丝编程路径

    公开(公告)号：US07173855B2

    公开(公告)日：2007-02-06

    申请号：US10930526

    申请日：2004-08-31

    申请人： Stephen R. Porter ,  Scott J. Derner

    发明人： Stephen R. Porter ,  Scott J. Derner

    IPC分类号： G11C11/34

    CPC分类号： H01L23/5252 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Method and apparatus are disclosed for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.

    摘要翻译： 公开了通过轻度掺杂电连接区域来调节反熔丝编程电流的方法和装置，使得区域的电阻以非线性方式响应于电压变化。 以这种方式，可以产生可变电阻器或可变电阻晶体管，其响应于施加的电压而改变其电阻，并且因此可限制编程电流，而不限制对串行连接的反熔丝的较小的读取电流。