公开(公告)号：US5691547A

公开(公告)日：1997-11-25

申请号：US376866

申请日：1995-01-23

Applicant: Monte Manning ,  Charles Dennison

Inventor： Monte Manning ,  Charles Dennison

IPC: H01L21/8244 ,  H01L27/11 ,  H01L29/76

CPC classification number: H01L27/11 ,  H01L27/1108 ,  Y10S257/903

Abstract: The disclosure includes preferred semiconductor transistor devices utilizing thin film transistors, as well as preferred methods of forming such devices. Specifically, a bottom thin film transistor gate is formed having a top surface. An insulating filler is provided adjacent the thin film transistor gate to an elevation at least as high as the thin film transistor gate top surface, and subsequently levelled to provide generally planar insulating surfaces adjacent the thin film transistor gate. The planar insulating surfaces are substantially coplanar with the thin film transistor gate top surface. A planar semiconductor thin film is then formed over the thin film transistor gate and over the adjacent planar insulating surfaces. The thin film is doped to form source and drain regions of a thin film transistor which is bottom gated by the thin film transistor gate.

Abstract translation: 本公开包括使用薄膜晶体管的优选半导体晶体管器件以及形成这种器件的优选方法。 具体地，形成具有顶表面的底部薄膜晶体管栅极。 在薄膜晶体管栅极附近提供绝缘填充物，至少与薄膜晶体管栅极顶表面一样高，并且随后平整以提供与薄膜晶体管栅极相邻的大致平面的绝缘表面。 平面绝缘表面基本上与薄膜晶体管栅极顶表面共面。 然后在薄膜晶体管栅极上方并在相邻的平面绝缘表面上形成平面半导体薄膜。 掺杂薄膜以形成薄膜晶体管的源区和漏极区，薄膜晶体管是由薄膜晶体管栅极选通的。

公开(公告)号：US08363446B2

公开(公告)日：2013-01-29

申请号：US12578638

申请日：2009-10-14

Applicant: Wolodymyr Czubatyj ,  Tyler Lowrey ,  Charles Dennison ,  Carl Schell

Inventor： Wolodymyr Czubatyj ,  Tyler Lowrey ,  Charles Dennison ,  Carl Schell

IPC: G11C11/00

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: A method of programming an electrical variable resistance memory device. When applied to variable resistance memory devices that incorporate a phase-change material as the active material, the method utilizes a plurality of crystalline programming states. The crystalline programming states are distinguishable on the basis of resistance, where the resistance values of the different states are stable with time and exhibit little or no drift. As a result, the programming scheme is particularly suited to multilevel memory applications. The crystalline programming states may be achieved by stabilizing crystalline phases that adopt different crystallographic structures or by stabilizing crystalline phases that include mixtures of two or more distinct crystallographic structures that vary in the relative proportions of the different crystallographic structures. The programming scheme incorporates at least two crystalline programming states and further includes at least a third programming state that may be a crystalline, amorphous or mixed crystalline-amorphous state.

Abstract translation: 一种编程电可变电阻存储器件的方法。 当应用于包含相变材料作为活性材料的可变电阻存储器件时，该方法利用多个晶体编程状态。 结晶编程状态可以根据电阻进行区分，其中不同状态的电阻值随时间稳定并且表现出很小的或没有漂移。 因此，编程方案特别适用于多层存储器应用。 晶体编程状态可以通过稳定采用不同晶体结构的结晶相或通过稳定结晶相来实现，所述结晶相包括两种或更多种不同结晶学结构的混合物，其在不同结晶学结构的相对比例中变化。 编程方案包含至少两个晶体编程状态，并且还包括至少第三编程状态，其可以是晶体，无定形或混合晶体 - 非晶状态。

公开(公告)号：US20070055818A1

公开(公告)日：2007-03-08

申请号：US11595370

申请日：2006-11-08

Applicant: Brent Keeth ,  Brian Shirley ,  Charles Dennison

Inventor： Brent Keeth ,  Brian Shirley ,  Charles Dennison

IPC: G06F13/28

CPC classification number: G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

Abstract: A cache memory system and method includes a DRAM having a plurality of banks, each of which may be refreshed under control of a refresh controller. In addition to the usual components of a DRAM, the cache memory system also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in the second bank. If, however, the second bank is being refreshed, the data are stored in the other SRAM. By the time data have been stored in the SRAM, the SRAM previously used to store write data has transferred the data to the first DRAM bank and in thus available to store a subsequent write. Therefore, an SRAM bank is always available to store write data in the event the DRAM bank to which the data are directed is being refreshed.

Abstract translation: 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，每个存储体可以在刷新控制器的控制下刷新。 除了DRAM的通常部件之外，高速缓冲存储器系统还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传送期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体中。 然而，如果第二个银行被刷新，则数据被存储在另一个SRAM中。 在数据已经存储在SRAM中的时候，先前用于存储写入数据的SRAM已将数据传送到第一DRAM存储体，并因此可用于存储随后的写入。 因此，在刷新数据所指向的DRAM组的情况下，SRAM存储体总是可用于存储写入数据。

公开(公告)号：US20060015679A1

公开(公告)日：2006-01-19

申请号：US11230836

申请日：2005-09-19

Applicant: Brent Keeth ,  Brian Shirley ,  Charles Dennison

Inventor： Brent Keeth ,  Brian Shirley ,  Charles Dennison

IPC: G06F12/00

CPC classification number: G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

公开(公告)号：US20050181567A1

公开(公告)日：2005-08-18

申请号：US11094377

申请日：2005-03-31

Applicant: Mark Fischer ,  Charles Dennison ,  Fawad Ahmed ,  Richard Lane ,  John Zahurak ,  Kunal Parekh

Inventor： Mark Fischer ,  Charles Dennison ,  Fawad Ahmed ,  Richard Lane ,  John Zahurak ,  Kunal Parekh

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8244

CPC classification number: H01L21/2652 ,  H01L21/2658 ,  H01L21/28247 ,  H01L29/6656 ,  H01L29/6659

Abstract: A double blanket ion implant method for forming diffulsion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffulsion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.

Abstract translation: 公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成差分区域的双层离子注入方法。 该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一覆盖离子注入工艺在与沟道区相邻的区域中形成第一对差分区域。 第一次毯式离子注入工艺具有第一能级和剂量。 该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。 在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。 第二次毯子离子注入过程具有第二能量水平和剂量。 所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。 此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

公开(公告)号：US20050145850A1

公开(公告)日：2005-07-07

申请号：US11063688

申请日：2005-02-22

Applicant: Charles Dennison ,  Monte Manning

Inventor： Charles Dennison ,  Monte Manning

IPC: H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/786 ,  H01L29/04 ,  H01L23/48 ,  H01L29/10 ,  H01L29/15

CPC classification number: H01L29/6675 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78648 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract translation: 电互连方法包括：a）在半导体晶片上提供由绝缘材料隔开的两个导电层; b）蚀刻导电层和绝缘材料以限定和向外暴露每个导电层的侧壁; c）在蚀刻的导电层及其各自的侧壁上沉积导电材料; 以及d）各向异性蚀刻所述导电材料以限定将所述两个导电层电连接的导电侧壁连接件。 这样可用于制造薄膜晶体管和其他电路。

公开(公告)号：US20050124157A1

公开(公告)日：2005-06-09

申请号：US10971812

申请日：2004-10-22

Applicant: Tyler Lowrey ,  Charles Dennison

Inventor： Tyler Lowrey ,  Charles Dennison

IPC: H01L21/285 ,  H01L21/768 ,  H01L27/24 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/7685 ,  H01L21/28562 ,  H01L21/76888 ,  H01L27/24

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the dielectric, utilizing atomic layer deposition (ALD). A programmable material is formed on the electrode and a conductor is formed to the programmable material. In an aspect, a barrier is conformally deposited utilizing ALD, between the electrode and the programmable material.

Abstract translation: 在一方面，提供一种设置和重新编程可编程设备的状态的设备。 在一方面，提供了一种方法，使得通过暴露接触的电介质形成开口，接触形成在基底上。 利用原子层沉积（ALD）将电极保形地沉积在电介质的壁上。 可编程材料形成在电极上，导体形成可编程材料。 在一个方面，在电极和可编程材料之间利用ALD共形沉积屏障。

公开(公告)号：US06869883B2

公开(公告)日：2005-03-22

申请号：US10319214

申请日：2002-12-13

Applicant: Chien Chiang ,  Charles Dennison ,  Tyler Lowrey

Inventor： Chien Chiang ,  Charles Dennison ,  Tyler Lowrey

IPC: H01L45/00 ,  H01L21/311

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

Abstract: Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the phase changes. The heater may be coupled to an appropriate conductor.

Abstract translation: 在一些情况下，通过将相变材料层形成为平面构型，相变存储器可以表现出改善的性能和较低的成本。 可以在相变材料层的下方设置加热器，以适当地加热材料以引起相变。 加热器可以耦合到适当的导体。

公开(公告)号：US20050029627A1

公开(公告)日：2005-02-10

申请号：US10633886

申请日：2003-08-04

Applicant: Charles Dennison

Inventor： Charles Dennison

IPC: H01L27/24 ,  H01L29/06

CPC classification number: H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

Abstract: A damascene approach may be utilized to form an electrode to a lower conductive line in a phase change memory. The phase change memory may be formed of a plurality of isolated memory cells, each including a phase change memory threshold switch and a phase change memory storage element.

Abstract translation: 可以利用镶嵌方法在相变存储器中形成电极到下导电线。 相变存储器可以由多个隔离存储器单元形成，每个隔离存储单元包括相变存储器阈值开关和相变存储器存储元件。

公开(公告)号：US20050020090A1

公开(公告)日：2005-01-27

申请号：US10923060

申请日：2004-08-19

Applicant: Charles Dennison ,  Trung Doan

Inventor： Charles Dennison ,  Trung Doan

IPC: H01L21/768 ,  H01L21/44 ,  C23F1/00

CPC classification number: H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76829 ,  Y10S438/95 ,  Y10S438/97

Abstract: A process for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process including forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The process may be repeated during the formation of multilevel metal integrated circuits.

Abstract translation: 在集成电路和器件的制造中形成垂直触点的工艺。 该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。 该方法包括在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。 在形成多级金属集成电路期间可以重复该过程。