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11.发明授权Out-of-order checkpoint reclamation in a checkpoint processing and recovery core microarchitecture 有权检查点处理和恢复核心微架构中的无序检查点回收公开(公告)号：US09262170B2
公开(公告)日：2016-02-16
申请号：US13558750
申请日：2012-07-26
CPC分类号： G06F9/3836 , G06F9/3859 , G06F9/3863 , G06F11/1407
摘要： Reclaiming checkpoints in a system in an order that differs from the order when the checkpoints are created. Reclaiming the checkpoints includes: creating one or more checkpoints, each of which having an initial state using system resources and holding the checkpoints state; identifying the completion of all the instructions associated with the checkpoint; reassigning all the instructions associated with the identified checkpoint to an immediately preceding checkpoint; and freeing the resources associated with the identified checkpoint. The checkpoint is created when the instruction that is checked is a conditional branch having a direction that cannot be predicted with a predetermined confidence level.
摘要翻译： 以不同于创建检查点的顺序的顺序回收系统中的检查点。 回收检查点包括：创建一个或多个检查点，每个检查点具有使用系统资源的初始状态并保持检查点状态; 确定与检查点相关联的所有指令的完成; 将与所识别的检查点相关联的所有指令重新分配给紧接在前的检查点; 并释放与识别的检查点相关联的资源。 当检查的指令是具有不能以预定置信水平预测的方向的条件分支时，创建检查点。
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公开(公告)号：US08726313B2
公开(公告)日：2014-05-13
申请号：US13453105
申请日：2012-04-23
CPC分类号： H04N21/4147 , H04N21/4334 , H04N21/4622 , H04N21/47202 , H04N21/47214 , H04N21/4828 , H04N21/84
摘要： A device receives an identification of a series to schedule automatic recording of episodes that are currently airing or that will be airing in the future, receives an instruction to automatically retrieve previously aired episodes of the scheduled series based on the scheduling of the automatic recording of the episodes that are currently airing or that will be airing in the future. The device searches content, based on receipt of the instruction, to retrieve previously aired episodes of the scheduled series. The device records at least one episode of the scheduled series, and presents the recorded at least one episode of the scheduled series and the previously aired episodes of the scheduled series such that a user may select and play the at least one episode of the scheduled series or the previously aired episodes of the scheduled series.
摘要翻译： 一个装置接收一系列的标识，以便安排自动记录当前播放或将来播放的情节，接收一个指令，以便根据自动记录的调度自动检索预定序列的先前播放的剧集 目前正在播出或将来播出的剧集。 该设备根据该指令的接收来搜索内容以检索预定系列的以前播放的剧集。 所述设备记录所述预定系列的至少一个剧集，并且呈现所述预定系列的所记录的至少一个剧集和所述预定系列的先前播放的剧集，使得用户可以选择并播放所述预定系列的至少一个剧集 或预定系列的以前播出的剧集。
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13.发明申请Out-of-Order Checkpoint Reclamation in a Checkpoint Processing and Recovery Core Microarchitecture 有权检查点处理和恢复核心微体系结构中的无序检查点回收公开(公告)号：US20140032884A1
公开(公告)日：2014-01-30
申请号：US13558750
申请日：2012-07-26
IPC分类号： G06F9/312
CPC分类号： G06F9/3836 , G06F9/3859 , G06F9/3863 , G06F11/1407
摘要： Reclaiming checkpoints in a system in an order that differs from the order when the checkpoints are created. Reclaiming the checkpoints includes: creating one or more checkpoints, each of which having an initial state using system resources and holding the checkpoints state; identifying the completion of all the instructions associated with the checkpoint; reassigning all the instructions associated with the identified checkpoint to an immediately preceding checkpoint; and freeing the resources associated with the identified checkpoint. The checkpoint is created when the instruction that is checked is a conditional branch having a direction that cannot be predicted with a predetermined confidence level.
摘要翻译： 以不同于创建检查点的顺序的顺序回收系统中的检查点。 回收检查点包括：创建一个或多个检查点，每个检查点具有使用系统资源的初始状态并保持检查点状态; 确定与检查点相关联的所有指令的完成; 将与所识别的检查点相关联的所有指令重新分配给紧接在前的检查点; 并释放与识别的检查点相关联的资源。 当检查的指令是具有不能以预定置信水平预测的方向的条件分支时，创建检查点。
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14.发明申请公开(公告)号：US20130297853A1
公开(公告)日：2013-11-07
申请号：US13464084
申请日：2012-05-04
申请人： Ganesh Balakrishnan , Anil Krishna
发明人： Ganesh Balakrishnan , Anil Krishna
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F12/0246 , G06F2212/222 , G06F2212/40 , Y02D10/13
摘要： In a method for storing data in a flash memory array, the flash memory array includes a plurality of physical pages. The method includes receiving a request to perform a data access operation through a communication bus. The request includes data and a logical page address. The method further includes allocating one or more physical pages of the flash memory array to perform the data access operation. The method further includes, based on a historical usage data of the flash memory array, selectively encoding the data contained in the logical page into the one or more physical pages.
摘要翻译： 在将数据存储在闪存阵列中的方法中，闪存阵列包括多个物理页。 该方法包括通过通信总线接收执行数据访问操作的请求。 该请求包括数据和逻辑页面地址。 该方法还包括分配闪存阵列的一个或多个物理页面以执行数据访问操作。 该方法还包括基于闪速存储器阵列的历史使用数据，选择性地将包含在逻辑页面中的数据编码到一个或多个物理页面中。
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公开(公告)号：US08572325B2
公开(公告)日：2013-10-29
申请号：US12961798
申请日：2010-12-07
IPC分类号： G06F12/08
CPC分类号： G06F12/0871 , G06F2212/282
摘要： Embodiments of the invention are directed to optimizing the performance of a split disk cache. In one embodiment, a disk cache includes a primary region having a read portion and write portion and one or more smaller, sample regions also including a read portion and a write portion. The primary region and one or more sample region each have an independently adjustable ratio of a read portion to a write portion. Cached reads are distributed among the read portions of the primary and sample region, while cached writes are distributed among the write portions of the primary and sample region. The performance of the primary region and the performance of the sample region are tracked, such as by obtaining a hit rate for each region during a predefined interval. The read/write ratio of the primary region is then selectively adjusted according to the performance of the one or more sample regions.
摘要翻译： 本发明的实施例旨在优化分割盘高速缓存的性能。 在一个实施例中，磁盘高速缓存包括具有读取部分和写入部分的主区域以及还包括读取部分和写入部分的一个或多个更小的采样区域。 主区域和一个或多个采样区域各自具有读取部分与写入部分的独立可调比率。 高速缓存的读取分布在主要和采样区域的读取部分之间，而高速缓存的写入分布在主要和样本区域的写入部分之间。 跟踪主区域的性能和样本区域的性能，例如通过在预定义的间隔期间获得每个区域的命中率。 然后根据一个或多个样品区域的性能选择性地调节主区域的读/写比。
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公开(公告)号：US08364898B2
公开(公告)日：2013-01-29
申请号：US12358873
申请日：2009-01-23
申请人： Ganesh Balakrishnan , Anil Krishna
发明人： Ganesh Balakrishnan , Anil Krishna
CPC分类号： G06F12/0802 , G06F12/0808 , G06F12/0811 , G06F12/0864 , G06F12/123
摘要： A method and a system for utilizing less recently used (LRU) bits and presence bits in selecting cache-lines for eviction from a lower level cache in a processor-memory sub-system. A cache back invalidation (CBI) logic utilizes LRU bits to evict only cache-lines within a LRU group, following a cache miss in the lower level cache. In addition, the CBI logic uses presence bits to (a) indicate whether a cache-line in a lower level cache is also present in a higher level cache and (b) evict only cache-lines in the lower level cache that are not present in a corresponding higher level cache. However, when the lower level cache-line selected for eviction is also present in any higher level cache, CBI logic invalidates the cache-line in the higher level cache. The CBI logic appropriately updates the values of presence bits and LRU bits, following evictions and invalidations.
摘要翻译： 一种用于利用最近使用的（LRU）比特和存在比特来选择用于从处理器存储器子系统中的较低级高速缓存进行逐出的高速缓存线的方法和系统。 缓存返回无效（CBI）逻辑利用LRU位来驱逐LRU组内的高速缓存行，跟随低级缓存中的高速缓存未命中。 此外，CBI逻辑使用存在位来（a）指示较低级高速缓存中的高速缓存行是否也存在于较高级高速缓存中，并且（b）仅驱逐不存在的较低级高速缓存中的高速缓存行 在相应的较高级缓存中。 然而，当选择用于逐出的较低级高速缓存行也存在于任何更高级别的高速缓存中时，CBI逻辑使高级缓存中的高速缓存行无效。 驱逐和无效后，CBI逻辑适当地更新存在位和LRU位的值。
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公开(公告)号：US08200905B2
公开(公告)日：2012-06-12
申请号：US12192072
申请日：2008-08-14
申请人： Gordon Bernard Bell , Gordon Taylor Davis , Jeffrey Haskell Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
发明人： Gordon Bernard Bell , Gordon Taylor Davis , Jeffrey Haskell Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/6026
摘要： A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.
摘要翻译： 处理系统包括被配置为处理应用的存储器和第一核心。 第一个核心包括第一个缓存。 处理系统包括被配置为捕获错过第一核心中的第一高速缓存的应用程序的地址序列并将地址序列放置在存储阵列中的机制; 以及被配置为处理至少一个软件算法的第二核心。 所述至少一个软件算法利用来自存储阵列的地址序列来生成预取地址序列。 第二个核心将预取地址序列的预取请求发送到存储器以获得预取数据，并且如果请求，则将预取数据提供给第一核。
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公开(公告)号：US08140825B2
公开(公告)日：2012-03-20
申请号：US12185964
申请日：2008-08-05
CPC分类号： G06F12/0215
摘要： Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for different processes. The table comprises rows corresponding to banks of memory and columns corresponding to cores of a multi-core processing system. When a context switch signal is received, the system unsets a bit in a column corresponding to the core from which the process is to be context-switched out. If no other process is using a page opened by the process the page is closed.
摘要翻译： 公开了用于在预期上下文切换中选择性地关闭存储器中的页面的系统，方法和介质。 在一个实施例中，提供了用于跟踪不同进程的打开页面的表格。 该表包括与多核处理系统的核心相对应的存储体组和列的行。 当接收到上下文切换信号时，系统取消对应于该进程将上下文切换出的核心的列中的位。 如果没有其他进程正在使用页面打开的页面关闭。
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19.发明授权Apparatus and method for using branch prediction heuristics for determination of trace formation readiness 失效使用分支预测启发式方法确定痕量形成准备的装置和方法公开(公告)号：US07934081B2
公开(公告)日：2011-04-26
申请号：US11538831
申请日：2006-10-05
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
摘要翻译： 单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。 缓存中的跟踪行的形成在系统的初始操作中被延迟，以确保存储的跟踪线的质量。
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公开(公告)号：US20100037034A1
公开(公告)日：2010-02-11
申请号：US12185964
申请日：2008-08-05
IPC分类号： G06F12/10
CPC分类号： G06F12/0215
摘要： Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for different processes. The table comprises rows corresponding to banks of memory and columns corresponding to cores of a multi-core processing system. When a context switch signal is received, the system unsets a bit in a column corresponding to the core from which the process is to be context-switched out. If no other process is using a page opened by the process the page is closed.
摘要翻译： 公开了用于在预期上下文切换中选择性地关闭存储器中的页面的系统，方法和介质。 在一个实施例中，提供了用于跟踪不同进程的打开页面的表格。 该表包括与多核处理系统的核心相对应的存储体组和列的行。 当接收到上下文切换信号时，系统取消对应于该进程将上下文切换出的核心的列中的位。 如果没有其他进程正在使用页面打开的页面关闭。
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