公开(公告)号：US20230418573A1

公开(公告)日：2023-12-28

申请号：US18466589

申请日：2023-09-13

申请人： Altera Corporation

发明人： Alan Baker ,  Andrew Chaang Ling ,  Andrei Mihai Hagiescu Miriste

IPC分类号： G06F8/41 ,  G06F8/40 ,  G06F9/54 ,  G06F30/34 ,  G06F30/327

CPC分类号： G06F8/41 ,  G06F8/40 ,  G06F9/54 ,  G06F30/34 ,  G06F30/327 ,  G06F2115/08

摘要： Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.

公开(公告)号：US20230289319A1

公开(公告)日：2023-09-14

申请号：US18299662

申请日：2023-04-12

申请人： Altera Corporation

发明人： Gary Brian Wallichs ,  Keith Duwel ,  Cora Lynn Mau

IPC分类号： G06F13/42 ,  H04L69/14 ,  G06F5/06

CPC分类号： G06F13/4286 ,  H04L69/14 ,  G06F5/065 ,  H04L49/25

摘要： Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

公开(公告)号：US11669479B2

公开(公告)日：2023-06-06

申请号：US17711860

申请日：2022-04-01

申请人： Altera Corporation

发明人： Huy Ngo ,  Keith Duwel ,  David W. Mendel

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F5/06

CPC分类号： G06F13/4022 ,  G06F5/065 ,  G06F13/4018 ,  G06F13/4291 ,  G06F2205/067

摘要： Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

公开(公告)号：US11520394B2

公开(公告)日：2022-12-06

申请号：US15889566

申请日：2018-02-06

申请人： Altera Corporation

发明人： Krishnan Venkataraman

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F1/329

摘要： Systems and methods are provided for reducing power consumption of a multi-die device, such as a network processor FPGA (npFPGA). The multi-die device may include hardware resources such as FPGA dies, which may be coupled to NIC dies and/or memory dies. Power consumption of the multi-die device may be reduced by monitoring usage of hardware resources in the multi-die device, identifying hardware resources that are not in use, and gating power to the identified hardware resources. The status of processing elements (PEs) in the multi-die device may be tracked in a PE state table. Based on the PE state table, tasks from a task queue may be assigned to one or more processing elements.

公开(公告)号：US11334504B2

公开(公告)日：2022-05-17

申请号：US16896157

申请日：2020-06-08

申请人： Altera Corporation

发明人： Steven Perry

IPC分类号： G06F13/16 ,  H03K19/17728 ,  H03K19/17748 ,  H03K19/17736 ,  G06F30/34 ,  G06F30/327 ,  H03K19/1776 ,  G06F13/42

摘要： Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input ports.

公开(公告)号：US20220137986A1

公开(公告)日：2022-05-05

申请号：US17403627

申请日：2021-08-16

申请人： Altera Corporation

发明人： Chee Hak Teh ,  Kenneth Chong Yin Tan

IPC分类号： G06F9/445 ,  G06F9/50

摘要： A method for dynamically configuring multiple processors based on needs of applications includes receiving, from an application, an acceleration request message including a task to be accelerated. The method further includes determining a type of the task and searching a database of available accelerators to dynamically select a first accelerator based on the type of the task. The method further includes sending the acceleration request message to a first acceleration interface located at a configurable processing circuit. The first acceleration interface sends the acceleration request message to a first accelerator, and the first accelerator accelerates the task upon receipt of the acceleration request message.

公开(公告)号：US11194757B2

公开(公告)日：2021-12-07

申请号：US17037642

申请日：2020-09-29

申请人： Altera Corporation

发明人： Chee Hak Teh ,  Arifur Rahman

IPC分类号： G06F15/78 ,  G06F13/00 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F1/06 ,  G06F1/10

摘要： A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US11137983B2

公开(公告)日：2021-10-05

申请号：US16586693

申请日：2019-09-27

申请人： Altera Corporation

发明人： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Hyun Yi

IPC分类号： G06F7/483 ,  G06F7/544 ,  G06F7/485 ,  G06F7/487 ,  G06F7/499

摘要： Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.

公开(公告)号：US20210109882A1

公开(公告)日：2021-04-15

申请号：US17131474

申请日：2020-12-22

申请人： Altera Corporation

发明人： Huy Ngo ,  Keith Duwel ,  David W. Mendel

IPC分类号： G06F13/40 ,  G06F5/06 ,  G06F13/42

摘要： Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

公开(公告)号：US10963291B2

公开(公告)日：2021-03-30

申请号：US16683093

申请日：2019-11-13

申请人： Altera Corporation

发明人： Abdel Hafiz Rabi ,  Allen Chen ,  Mark Jonathan Lewis ,  Jiefan Zhang

IPC分类号： G06F13/40 ,  G06F9/455 ,  G06F13/28

摘要： A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.