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1.发明申请MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE, DEDICATED CONNECTIONS BETWEEN MODULES OF THE CIRCUITRY 有权模块化数字信号处理电路，具有可选择的电路模块之间的专用连接公开(公告)号：US20140082035A1
公开(公告)日：2014-03-20
申请号：US14086328
申请日：2013-11-21
申请人： Altera Corporation
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lui , Suleyman Sirri Demirsoy , Hyun Yi
IPC分类号： G06F17/10
CPC分类号： G06F17/10 , G06F7/5324 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
摘要翻译： 提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。 尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。 收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。
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2.发明申请MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE, DEDICATED CONNECTIONS BETWEEN MODULES OF THE CIRCUITRY 有权模块化数字信号处理电路，具有可选择的电路模块之间的专用连接公开(公告)号：US20130332497A1
公开(公告)日：2013-12-12
申请号：US13961534
申请日：2013-08-07
申请人： Altera Corporation
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lui , Suleyman Sirri Demirsoy , Hyun Yi
IPC分类号： G06F17/10
CPC分类号： G06F17/10 , G06F7/5324 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
摘要翻译： 提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。 尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。 收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。
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3.发明授权公开(公告)号：US11137983B2
公开(公告)日：2021-10-05
申请号：US16586693
申请日：2019-09-27
申请人： Altera Corporation
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Hyun Yi
摘要： Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.
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4.发明申请公开(公告)号：US20220027128A1
公开(公告)日：2022-01-27
申请号：US17493584
申请日：2021-10-04
申请人： Altera Corporation
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Hyun Yi
摘要： Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.
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5.发明申请公开(公告)号：US20200026493A1
公开(公告)日：2020-01-23
申请号：US16586693
申请日：2019-09-27
申请人： Altera Corporation
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Hyun Yi
摘要： Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.
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6.发明授权公开(公告)号：US10474429B1
公开(公告)日：2019-11-12
申请号：US15331024
申请日：2016-10-21
申请人： Altera Corporation
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Hyun Yi
摘要： Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.
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7.发明授权Programmable device implementing fixed and floating point functionality in a mixed architecture 有权在混合架构中实现固定和浮点功能的可编程设备公开(公告)号：US09507565B1
公开(公告)日：2016-11-29
申请号：US14180664
申请日：2014-02-14
申请人： Altera Corporation
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Hyun Yi
CPC分类号： G06F7/485 , G06F7/483 , G06F7/4876 , G06F7/499
摘要： Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.
摘要翻译： 描述了可配置的专用处理块，例如DSP块，其在可编程设备上的单个混合架构中实现固定和浮点功能。 所描述的架构减少了在可配置专用处理块之外构建浮点函数的需要，从而最小化硬件成本和面积。 所公开的架构还将流水线引入到DSP模块中，以确保浮点乘法和加法函数保持同步，从而增加DSP块可以工作的最大频率。 此外，所公开的架构包括支持浮点异常处理的逻辑电路。
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8.发明授权Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry 有权模块化数字信号处理电路，具有电路模块之间任意可用的专用连接公开(公告)号：US08751551B2
公开(公告)日：2014-06-10
申请号：US14086328
申请日：2013-11-21
申请人： Altera Corporation
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lui , Suleyman Sirri Demirsoy , Hyun Yi
CPC分类号： G06F17/10 , G06F7/5324 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
摘要翻译： 提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。 尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。 收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。
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公开(公告)号：US08620977B1
公开(公告)日：2013-12-31
申请号：US13961534
申请日：2013-08-07
申请人： Altera Corporation
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lui , Suleyman Sirri Demirsoy , Hyun Yi
CPC分类号： G06F17/10 , G06F7/5324 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
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