公开(公告)号：US20220238681A1

公开(公告)日：2022-07-28

申请号：US17717382

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.

公开(公告)号：US20220231124A1

公开(公告)日：2022-07-21

申请号：US17198650

申请日：2021-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02

Abstract: A method of forming semiconductor devices having improved work function layers and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes depositing a gate dielectric layer on a channel region over a semiconductor substrate; depositing a first p-type work function metal on the gate dielectric layer; performing an oxygen treatment on the first p-type work function metal; and after performing the oxygen treatment, depositing a second p-type work function metal on the first p-type work function metal.

公开(公告)号：US20220216307A1

公开(公告)日：2022-07-07

申请号：US17656738

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Hsin-Yi Lee ,  Ya-Huei Li ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L29/40 ,  H01L27/088 ,  H01L21/3215 ,  H01L21/8234 ,  H01L21/285 ,  H01L29/49

Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.

公开(公告)号：US11227931B2

公开(公告)日：2022-01-18

申请号：US16904751

申请日：2020-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device includes a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions. The gate structure includes: a gate dielectric material around each of the nanosheets; a first liner material around the gate dielectric material; a work function material around the first liner material; a second liner material around the work function material; and a gate electrode material around at least portions of the second liner material.

公开(公告)号：US20210391436A1

公开(公告)日：2021-12-16

申请号：US16943110

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L27/092

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.

公开(公告)号：US11121041B2

公开(公告)日：2021-09-14

申请号：US16684765

申请日：2019-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zoe Chen ,  Ching-Hwanq Su ,  Cheng-Lung Hung ,  Cheng-Yen Tsai ,  Da-Yuan Lee ,  Hsin-Yi Lee ,  Weng Chang ,  Wei-Chin Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10

Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.

公开(公告)号：US10658488B2

公开(公告)日：2020-05-19

申请号：US15978546

申请日：2018-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Yen Tsai ,  Da-Yuan Lee

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/285 ,  H01L27/088 ,  H01L21/67 ,  H01L29/51

Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.

公开(公告)号：US09978601B2

公开(公告)日：2018-05-22

申请号：US15192570

申请日：2016-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yen Tsai ,  Hsin-Yi Lee ,  Chung-Chiang Wu ,  Da-Yuan Lee ,  Weng Chang ,  Ming-Hsing Tsai

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/768 ,  C23C14/58 ,  C23C16/56 ,  C23C16/455

CPC classification number: H01L21/28105 ,  C23C14/58 ,  C23C14/5846 ,  C23C14/5873 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/02697 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/76838 ,  H01L21/76886

Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.