ENHANCED METHOD OF SENSING IONIZATION CURRENT IN SPARK IGNITION INTERNAL COMBUSTION ENGINES AND RELATED SPARK PLUG STRUCTURES
    142.
    发明申请
    ENHANCED METHOD OF SENSING IONIZATION CURRENT IN SPARK IGNITION INTERNAL COMBUSTION ENGINES AND RELATED SPARK PLUG STRUCTURES 有权
    火花点火内部燃烧发动机和相关火花喷射结构的感应电流的增强方法

    公开(公告)号:US20130099792A1

    公开(公告)日:2013-04-25

    申请号:US13654891

    申请日:2012-10-18

    CPC classification number: H01T13/40 F02P2017/125 H01T13/60 H01T21/02

    Abstract: A spark plug, including an insulator embedding a first metallic electrode axially extending therethrough from a high voltage outer end terminal to the center of the inner end of the insulator from which it protrudes; a metallic ground electrode isolated from the first electrode and having an extended inner termination facing toward the first electrode extending from the insulator tip for defining therebetween a spark gap, a resistive element connected to the ground electrode such that upon mounting the spark plug in an internal combustion engine, the ground electrode electrically connects to the engine body through the resistive element; and to a second outer termination of the ground electrode, adapted to constitute an accessible sensing terminal.

    Abstract translation: 一种火花塞,包括绝缘体,其嵌入从高压外端端子轴向延伸穿过其中突出的绝缘体的内端的中心的第一金属电极; 金属接地电极,与第一电极隔离并且具有面向从第一电极延伸的第一电极的延伸的内部端子,其从绝缘体末端延伸以在其间形成火花隙;电阻元件,连接到接地电极,使得在将火花塞安装在内部 内燃机,接地电极通过电阻元件电连接到发动机主体; 并且连接到接地电极的第二外部端子,适于构成可访问感测端子。

    INTEGRATED VOLTAGE DIVIDER
    143.
    发明申请
    INTEGRATED VOLTAGE DIVIDER 有权
    集成电压分压器

    公开(公告)号:US20130070429A1

    公开(公告)日:2013-03-21

    申请号:US13615220

    申请日:2012-09-13

    Abstract: A semiconductor structure including a high-voltage transistor; voltage dropping circuitry, at least part of which is overlapping the high-voltage transistor; at least one intermediate contact point to the voltage dropping circuitry, connected to at least one intermediate position between a first and a second end of the voltage dropping circuitry; and at least one external connection connecting the at least one intermediate contact point to outside of the semiconductor structure.

    Abstract translation: 一种包括高压晶体管的半导体结构; 降压电路,其至少一部分与高压晶体管重叠; 至少一个到所述降压电路的中间接触点,连接到所述降压电路的第一和第二端之间的至少一个中间位置; 以及将所述至少一个中间接触点连接到所述半导体结构外部的至少一个外部连接。

    IMAGE CHROMA NOISE REDUCTION
    144.
    发明申请
    IMAGE CHROMA NOISE REDUCTION 有权
    图像色彩降噪

    公开(公告)号:US20130064448A1

    公开(公告)日:2013-03-14

    申请号:US13608783

    申请日:2012-09-10

    Abstract: An embodiment of a method for reducing chroma noise in digital image data and of a corresponding image processor. Chrominance components are subjected to low-pass filtering. The strength of the low-pass filtering is modulated in accordance with the dynamic range of the luminance signal and the dynamic range of each of the two chrominance signals in order to avoid color bleeding at image-object edges. Moreover, the low-pass filtering is selectively applied to pixels with similar luminance and chrominance values only. A combination of down-sampling and up-sampling units is employed so that comparatively small filter kernels may be used for removing chroma noise with low spatial frequency.

    Abstract translation: 一种用于降低数字图像数据和对应的图像处理器中的色度噪声的方法的实施例。 色度分量经过低通滤波。 根据亮度信号的动态范围和两个色度信号中的每一个的动态范围来调制低通滤波的强度,以避免图像对象边缘的色彩渗透。 此外,低通滤波被选择性地应用于具有相似亮度和色度值的像素。 采用下采样和上采样单元的组合,使得可以使用较小的滤波器核来去除具有低空间频率的色度噪声。

    ANALYZER FOR BIOCHEMICAL ANALYSES AND METHOD OF DETERMINING CONCENTRATIONS OF FLUORESCENT SUBSTANCES IN A SOLUTION
    146.
    发明申请
    ANALYZER FOR BIOCHEMICAL ANALYSES AND METHOD OF DETERMINING CONCENTRATIONS OF FLUORESCENT SUBSTANCES IN A SOLUTION 有权
    生物化学分析仪分析仪和溶液中荧光物质浓度的测定方法

    公开(公告)号:US20130004954A1

    公开(公告)日:2013-01-03

    申请号:US13338777

    申请日:2011-12-28

    Abstract: An analyzer for biochemical analyses includes a seat for receiving a recipient. A first light source and a second light source illuminate the recipient with a luminous radiation, respectively, in a first excitation band and in a second excitation band, including a first excitation wavelength and a second excitation wavelength of fluorophores of a first type and of a second type. A first image sensor and a second image sensor are oriented so as to receive light emitted by fluorophores contained in the recipient and are, respectively, provided with a first detection filter and a second detection filter, having, respectively, a first detection passband and a second detection passband, including, respectively, a first emission wavelength and a second emission wavelength of the fluorophores of the first type and of the second type.

    Abstract translation: 用于生化分析的分析仪包括用于接收接收者的座位。 第一光源和第二光源分别在第一激发频带和第二激励频带中分别照射具有发光的接收器,所述第一激发频带和第二激励频带包括第一类型的荧光团的第一激发波长和第二激发波长, 第二种。 第一图像传感器和第二图像传感器被定向为接收容纳在接收器中的荧光团发射的光,并且分别具有第一检测滤波器和第二检测滤波器,第一检测滤波器和第二检测滤波器分别具有第一检测通带和 第二检测通带,分别包括第一类型和第二类型的荧光团的第一发射波长和第二发射波长。

    SEQUENCE ARBITER FOR ANALOG-TO-DIGITAL CONVERSIONS
    147.
    发明申请
    SEQUENCE ARBITER FOR ANALOG-TO-DIGITAL CONVERSIONS 有权
    用于模拟数字转换的序列ARBITER

    公开(公告)号:US20120299760A1

    公开(公告)日:2012-11-29

    申请号:US13467564

    申请日:2012-05-09

    CPC classification number: H03M1/122

    Abstract: An analog-to-digital converter device may include an input multiplexer circuit having analog input terminals configured to receive a respective plurality of analog input signals. The input multiplexer circuit may be responsive to a first select input. The device may also include a trigger multiplexer circuit having input terminals configured to receive respective triggering signals. The trigger multiplexer circuit may be responsive to a second select input. Analog-to-digital converter circuitry may be configured to convert the selected analog signal into a digital signal. A sequence arbiter may be coupled to the first and second select inputs and may have input terminals configured to receive a respective plurality of conversion sequence configuration signals. The sequence arbiter may be configured to manage each conversion sequence of the analog-to-digital converter circuitry based upon the relative conversion sequence configuration signal received, and control the conversion sequences.

    Abstract translation: 模拟 - 数字转换器装置可以包括具有被配置为接收相应的多个模拟输入信号的模拟输入端的输入多路复用器电路。 输入多路复用器电路可以响应于第一选择输入。 该装置还可以包括具有被配置为接收相应的触发信号的输入端的触发多路复用器电路。 触发多路复用器电路可以响应于第二选择输入。 模数转换器电路可以被配置为将所选择的模拟信号转换为数字信号。 序列仲裁器可以耦合到第一和第二选择输入,并且可以具有被配置为接收相应的多个转换序列配置信号的输入端子。 序列仲裁器可以被配置为基于接收到的相对转换序列配置信号来管理模数转换器电路的每个转换序列,并且控制转换序列。

    ELECTRONIC TRIMMING CIRCUIT
    148.
    发明申请
    ELECTRONIC TRIMMING CIRCUIT 有权
    电子修剪电路

    公开(公告)号:US20120286848A1

    公开(公告)日:2012-11-15

    申请号:US13468355

    申请日:2012-05-10

    CPC classification number: H01L27/0629 H01C17/22

    Abstract: The trimming circuit includes a plurality of trimmable resistances that may be coupled among them, each resistance being connected in parallel to a respective fuse. The trimming circuit allows burning any number of fuses according to a fixed trimming sequence using only one or two dedicated pins because it includes an input diode-connected transistor and a plurality of trimming transistors of different sectional area, each connected to force current throughout a respective one of the shunt fuses and coupled to the input diode-connected transistor such to mirror the current flowing therethrough. The fuses of the trimming circuit may be burnt by applying a trimming voltage to the diode-connected input transistor with a voltage generator connected between a dedicated pin of the circuit and a terminal at a reference potential, such to force a current therethrough as long as the mirrored currents flowing throughout the fuses burn them.

    Abstract translation: 修整电路包括可以在它们之间耦合的多个可调节电阻,每个电阻并联连接到相应的保险丝。 修整电路允许使用仅一个或两个专用引脚根据固定的修整顺序烧制任何数量的保险丝,因为它包括输入二极管连接的晶体管和多个不同截面面积的修整晶体管,每个都与各自的 分流熔丝之一并且耦合到输入二极管连接的晶体管,以反射流过其中的电流。 修整电路的熔丝可以通过在连接在电路的专用引脚和参考电位的端子之间的电压发生器对二极管连接的输入晶体管施加修整电压而被烧,从而只要 在整个保险丝中流动的镜像电流会烧毁它们。

    SYSTEMS AND METHODS FOR REAL-TIME LOCATION
    149.
    发明申请
    SYSTEMS AND METHODS FOR REAL-TIME LOCATION 有权
    用于实时位置的系统和方法

    公开(公告)号:US20120077513A1

    公开(公告)日:2012-03-29

    申请号:US13221797

    申请日:2011-08-30

    CPC classification number: H04W64/00 G01S5/14 H04W84/18

    Abstract: An embodiment concerns the field of real-time location systems (RTLS) based on RSSI (Received Signal Strength Indication) measurements. An embodiment is based on determining the distances between wireless device of a network based on a model that describes the relation of the RSSI value relative to the packet exchanged between nodes as a function of the distance, wherein said model depends on at least one characteristic parameter of the transmission channel and wherein at least said characteristic parameter of the transmission channel is determined periodically and automatically, exploiting the known distances among fixed nodes. In this way, the errors relative to possible time-variability of the transmission channel are reduced and the accuracy and stability of the location measurements are increased.

    Abstract translation: 实施例涉及基于RSSI(接收信号强度指示)测量的实时定位系统(RTLS)领域。 一个实施例是基于基于描述RSSI值相对于在节点之间交换的分组之间的关系的模型来确定网络的无线设备之间的距离作为距离的函数,其中所述模型依赖于至少一个特征参数 并且其中定期和自动地确定传输信道的至少所述特征参数,利用固定节点之间的已知距离。 以这种方式,相对于传输通道的可能的时间变化性的误差减小,并且位置测量的精度和稳定性增加。

    MEMORY BASE CELL AND MEMORY BANK
    150.
    发明申请
    MEMORY BASE CELL AND MEMORY BANK 有权
    存储基础单元和存储器银行

    公开(公告)号:US20120075920A1

    公开(公告)日:2012-03-29

    申请号:US13097502

    申请日:2011-04-29

    CPC classification number: G11C11/412 Y10T29/49069

    Abstract: A memory base cell stores a bit of information implemented from a regular and compact structure made up of multiple identical and replicated base elements, on the “sea of gates” Model, in which the base element of the structure is a cell able to be configured with a minimum width in relation to the particular technology used. Such a cell includes a bistable element with an input node operatively connected to a writing data line of the memory base cell, and an output node operatively connected to a reading data line of the memory base cell. The bistable element also has a first inverter and a second inverter arranged in a feedback configuration with respect to one another between the input node and the output node of the bistable element.

    Abstract translation: 存储器基座存储从“多数相同和复制的基本元件”构成的规则紧凑的结构实现的信息位,在“海上大门”模型中,其中该结构的基本元件是能够被配置的单元 相对于所使用的特定技术具有最小宽度。 这种单元包括双稳态元件,其输入节点可操作地连接到存储器基本单元的写入数据线,以及可操作地连接到存储器基本单元的读取数据线的输出节点。 双稳态元件还具有在双稳态元件的输入节点和输出节点之间相对于彼此布置成反馈配置的第一反相器和第二反相器。

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