公开(公告)号：US11158750B2

公开(公告)日：2021-10-26

申请号：US16502108

申请日：2019-07-03

Applicant: Texas Instruments Incorporated

Inventor： He Lin ,  Sameer Pendharkar

IPC: H01L31/0352 ,  H01L31/0224 ,  H01L31/0216 ,  H01L31/02 ,  H01L27/144 ,  H01L31/103 ,  H01L31/0304 ,  H01L25/04 ,  H01L31/18

Abstract: A photo detector includes a superlattice with an undoped first semiconductor layer including undoped intrinsic semiconductor material, a doped second semiconductor layer having a first conductivity type on the first semiconductor layer, an undoped third semiconductor layer including undoped intrinsic semiconductor material on the second semiconductor layer, and a fourth semiconductor layer having a second opposite conductivity type on the third semiconductor layer, along with a first contact having the first conductivity type in the first, second, third, and fourth semiconductor layers, and a second contact having the second conductivity type and spaced apart from the first contact in the first, second, third, and fourth semiconductor layers. An optical shield on a second shielded portion of a top surface of the fourth semiconductor layer establishes electron and hole lakes. A packaging structure includes an opening that allows light to enter an exposed first portion of the top surface of the fourth semiconductor layer.

公开(公告)号：US20210167206A1

公开(公告)日：2021-06-03

申请号：US17174023

申请日：2021-02-11

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  David LaFonteese

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a p-channel device and an n-channel device. The p-channel device includes an n-type barrier region circumscribing a p-type drain region with an n-type body region. The p-channel device may be positioned adjacent to the n-channel device and a high voltage junction diode.

公开(公告)号：US10896904B2

公开(公告)日：2021-01-19

申请号：US16677044

申请日：2019-11-07

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  David LaFonteese ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/732 ,  H01L29/40

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

公开(公告)号：US10680093B2

公开(公告)日：2020-06-09

申请号：US15864157

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo Joh ,  Naveen Tipirneni ,  Chang Soo Suh ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L29/06 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

公开(公告)号：US10571511B2

公开(公告)日：2020-02-25

申请号：US16130035

申请日：2018-09-13

Applicant: Texas Instruments Incorporated

Inventor： Alex Paikin ,  Colin Johnson ,  Tathagata Chatterjee ,  Sameer Pendharkar

IPC: G01R31/10 ,  G01R31/26 ,  G01R31/28

Abstract: In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.

公开(公告)号：US20190237535A1

公开(公告)日：2019-08-01

申请号：US16379165

申请日：2019-04-09

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Binghua Hu ,  Sameer Pendharkar

IPC: H01L49/02 ,  H01L23/535 ,  H01L21/311 ,  H01L21/283 ,  H01L21/768

CPC classification number: H01L28/60 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/76895 ,  H01L23/535

Abstract: An integrated trench capacitor and method for making the trench capacitor is disclosed. The method includes forming a trench in a silicon layer, forming a first dielectric on the exposed surface of the trench, performing an anisotropic etch of the first dielectric to expose silicon at the bottom of the trench, implanting a dopant into exposed silicon at the bottom of the trench, forming a first polysilicon layer over the first dielectric, forming a second dielectric over the first polysilicon layer, and forming a second polysilicon layer over the second dielectric to fill the trench.

公开(公告)号：US20190198666A1

公开(公告)日：2019-06-27

申请号：US15850854

申请日：2017-12-21

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L21/761 ,  H01L21/28 ,  H03K17/687

Abstract: A lateral junction diode device includes a substrate having at least a semiconductor surface layer. A depletion-mode LDMOS device is in the semiconductor surface layer including a source, drain, and a gate above a gate dielectric, and a channel region under the gate on the gate dielectric. A drift region is between the channel region and the drain, wherein the drain also provides a cathode for the lateral junction diode device. An embedded diode includes a second cathode and an anode that is shared with the device. The embedded diode is junction isolated by an isolation region located between the anode and the source. The anode and isolation region are directly connected to the gate and the second cathode is directly connected to the source.

公开(公告)号：US10312095B1

公开(公告)日：2019-06-04

申请号：US16163602

申请日：2018-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Yoshikazu Kondo ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/205 ,  H01L21/28 ,  H01L29/423 ,  H01L21/02 ,  H01L29/778 ,  H01L29/51 ,  H01L29/66 ,  H01L29/20

Abstract: An electronic device, that in various embodiments includes a first semiconductor layer comprising a first group III nitride. A second semiconductor layer is located directly on the first semiconductor layer and comprises a second different group III nitride. A cap layer comprising the first group III nitride is located directly on the second semiconductor layer. A dielectric layer is located over the cap layer and directly contacts the second semiconductor layer through an opening in the cap layer.

公开(公告)号：US10290699B2

公开(公告)日：2019-05-14

申请号：US15245511

申请日：2016-08-24

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Binghua Hu ,  Sameer Pendharkar

IPC: H01L49/02 ,  H01L21/283 ,  H01L21/311 ,  H01L21/768 ,  H01L23/535

Abstract: An integrated trench capacitor and method for making the trench capacitor is disclosed. The method includes forming a trench in a silicon layer, forming a first dielectric on the exposed surface of the trench, performing an anisotropic etch of the first dielectric to expose silicon at the bottom of the trench, implanting a dopant into exposed silicon at the bottom of the trench, forming a first polysilicon layer over the first dielectric, forming a second dielectric over the first polysilicon layer, and forming a second polysilicon layer over the second dielectric to fill the trench.

公开(公告)号：US20180175191A1

公开(公告)日：2018-06-21

申请号：US15830263

申请日：2017-12-04

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Ming-yeh Chuang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/66689

Abstract: A power transistor is provided with at least one transistor finger that lies within a semiconductor material. The gate oxide is segmented into a set of segments with thick field oxide between each segment in order to reduce gate capacitance and thereby improve a resistance times gate charge figure of merit.