公开(公告)号：US08756446B2

公开(公告)日：2014-06-17

申请号：US12933229

申请日：2008-04-11

申请人： Vianney Rancurel ,  Vincent Bufferne ,  Gregory Meunier

发明人： Vianney Rancurel ,  Vincent Bufferne ,  Gregory Meunier

IPC分类号： G06F1/00 ,  G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00 ,  G06F1/04 ,  G06F1/14 ,  G06F5/06

CPC分类号： G06F1/3203 ,  G06F1/324 ,  Y02D10/126

摘要： A microprocessor has a low-power mode and a non-low power mode. The microprocessor includes a processor core for executing instructions provided to the microprocessor and a clock providing a clock signal, which in the non-low power mode has a first frequency and in the low power mode has a second frequency lower than the first frequency. A hardware timer is present, for scheduling an execution of an event by the microprocessor at a future point in time. The hardware timer is connected to the clock for determining a period of time between a current point in time and a point in time the event based on a number of clock cycles of the clock signal. A timer controller can determine, when the data processing system switches from the low power mode to the non-low power mode, a number of clock cycles of a clock signal with the first frequency that corresponds to a low-power mode period during which the microprocessor has been in the low power mode and adjusting the hardware timer based on the determined number.

摘要翻译： 微处理器具有低功率模式和非低功耗模式。 微处理器包括用于执行提供给微处理器的指令的处理器核心和提供时钟信号的时钟，该时钟信号在非低功率模式中具有第一频率，低功率模式具有低于第一频率的第二频率。 存在硬件定时器，用于在未来的时间点调度微处理器执行事件。 硬件定时器连接到时钟，用于基于时钟信号的时钟周期数来确定当前时间点和事件的时间点之间的时间段。 定时器控制器可以确定当数据处理系统从低功率模式切换到非低功率模式时，具有对应于低功率模式周期的第一频率的时钟信号的数个时钟周期， 微处理器已经处于低功耗模式，并根据确定的数量调整硬件定时器。

公开(公告)号：US08732514B2

公开(公告)日：2014-05-20

申请号：US13784519

申请日：2013-03-04

申请人： Microsoft Corporation

发明人： Nicholas A. Allen ,  Justin D. Brown

IPC分类号： G06F1/04 ,  G06F5/06 ,  G06F9/46

CPC分类号： G06F1/08 ,  G06F1/04 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126

摘要： Clock pulses of a variable speed clock are adjusted relative to system utilization. A load monitor periodically collects sensor measurements of resources and based on the sensor measurements, the load monitor adjusts the clock speed up or down.

摘要翻译： 可变速度时钟的时钟脉冲相对于系统利用率进行调整。 负载监视器定期收集资源的传感器测量值，并根据传感器测量结果，负载监视器可以上下调节时钟速度。

公开(公告)号：US20140115201A1

公开(公告)日：2014-04-24

申请号：US14143101

申请日：2013-12-30

申请人： Huawei Technologies Co., Ltd.

发明人： Chunlei Fan ,  Zhuo Chen ,  Renjie Qu

IPC分类号： G06F5/06

CPC分类号： G06F5/065 ,  G06F5/06

摘要： Embodiments of the present invention relate to a signal order-preserving method and apparatus. When data of a request signal that comes from a corresponding first upstream device is written into a first first input first output (FIFO) memory, invalid data is written into a second FIFO memory corresponding to a second upstream device in a same clock cycle; and the data of the request signal is read from the first FIFO memory, the invalid data is read from the second FIFO memory, the invalid data is discarded, and the data of the request signal is conveyed to a downstream device. Through the signal order-preserving method and apparatus in the embodiments of the present invention, the coupling extent between devices on which there is an order-preserving requirement is reduced while signal order-preserving is achieved.

摘要翻译： 本发明的实施例涉及信号顺序保存方法和装置。 当来自相应的第一上游设备的请求信号的数据被写入到第一第一输入第一输出（FIFO）存储器中时，无效数据以相同的时钟周期写入对应于第二上游设备的第二FIFO存储器中; 并且从第一FIFO存储器读取请求信号的数据，从第二FIFO存储器读取无效数据，丢弃无效数据，并将请求信号的数据传送到下游设备。 通过本发明的实施例中的信号顺序保存方法和装置，减少了维持信号顺序的装置之间的耦合范围。

公开(公告)号：US08612786B1

公开(公告)日：2013-12-17

申请号：US12890003

申请日：2010-09-24

申请人： Manish Lachwani ,  David Berbessou

发明人： Manish Lachwani ,  David Berbessou

IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F1/12 ,  G06F5/06

CPC分类号： G06F1/3228 ,  G06F1/324 ,  Y02D10/126 ,  Y02D50/20

摘要： A deep idle mode for electronic devices is described, which provides significant power savings while allowing significantly shorter resumption times than experienced with a suspend mode. During deep idle mode, a root clock such as the microcontroller unit phase-locked loop (MPLL) is scaled or gated entirely and other clocks such as the processor, memory, and general purpose timer clocks may be scaled. To maintain functionality while these clocks are scaled or gated, an external clock source couples to the processor, memory, and a general purpose timer.

摘要翻译： 描述了用于电子设备的深空闲模式，其提供显着的功率节省，同时允许比暂停模式经历的显着更短的恢复时间。 在深空闲模式期间，诸如微控制器单元锁相环（MPLL）的根时钟被完全缩放或门控，并且诸如处理器，存储器和通用定时器时钟的其他时钟可以被缩放。 为了在这些时钟被缩放或门控时保持功能，外部时钟源耦合到处理器，存储器和通用定时器。

公开(公告)号：US08601178B2

公开(公告)日：2013-12-03

申请号：US13555805

申请日：2012-07-23

申请人： Lisa D. Amini ,  Anshul Sehgal ,  Jeremy I. Silber ,  Olivier Verscheure

发明人： Lisa D. Amini ,  Anshul Sehgal ,  Jeremy I. Silber ,  Olivier Verscheure

IPC分类号： G06F5/06

CPC分类号： H04L29/06027 ,  H04L47/10 ,  H04L47/125 ,  H04L47/30 ,  H04L65/80

摘要： Disclosed are a method and a computer program storage product for dynamically stabilizing a stream processing system. The method includes receiving at least one computing resource allocation target. A plurality of downstream processing elements and an upstream processing element are associated with at least one input buffer. Each of the downstream processing elements consumes data packets produced by the upstream processing element received on an output stream associated with the upstream processing element. A fastest input rate among each downstream processing element in the plurality of downstream processing elements is identified. An output rate of the upstream processing element is set to the fastest input rate that has been determined for the plurality of downstream processing elements.

摘要翻译： 公开了一种用于动态稳定流处理系统的方法和计算机程序存储产品。 该方法包括接收至少一个计算资源分配目标。 多个下游处理元件和上游处理元件与至少一个输入缓冲器相关联。 每个下游处理单元消耗由与上游处理单元相关联的输出流上接收的上游处理单元生成的数据分组。 识别多个下游处理元件中的每个下游处理元件之间的最快输入速率。 上游处理单元的输出速率被设定为已经为多个下游处理单元确定的最快的输入速率。

公开(公告)号：US08514654B2

公开(公告)日：2013-08-20

申请号：US12875773

申请日：2010-09-03

申请人： Shinichi Yamada ,  Yasuhiko Kosugi ,  Noboru Asauchi ,  Yoshihiro Nakamura

发明人： Shinichi Yamada ,  Yasuhiko Kosugi ,  Noboru Asauchi ,  Yoshihiro Nakamura

IPC分类号： G11C7/22 ,  G11C8/18 ,  G11C7/24 ,  G11C8/20 ,  G11C5/14 ,  G06F1/12 ,  G06F1/04 ,  G06F11/30 ,  G06F5/06

CPC分类号： G11C5/143 ,  G11C8/18

摘要： A storage apparatus including a nonvolatile storage section and a control section controlling the nonvolatile storage section, wherein the control section has a detection circuit detecting floating state in at least one of power supply terminal connected to host side power supply terminal to which a power supply voltage is supplied from the host device, and ground terminal connected to host side ground terminal to which a ground voltage is supplied from the host device and a mask process section performing a mask process of the system clock that is used to control the nonvolatile storage section, wherein the mask process section masks the system clock if the floating state is detected by the detection circuit.

摘要翻译： 一种存储装置，包括非易失性存储部分和控制非易失性存储部分的控制部分，其中所述控制部分具有检测电路，该检测电路检测与连接到主机侧电源端子的电源端子中的至少一个中的浮动状态， 从主机装置供给接地端子，接地端子与主机装置提供接地电压的主机侧接地端子连接;以及屏蔽处理部件，对屏蔽处理部分进行用于控制非易失性存储部件的系统时钟， 其中如果检测电路检测到浮动状态，则掩模处理部分屏蔽系统时钟。

公开(公告)号：US08452908B2

公开(公告)日：2013-05-28

申请号：US12648373

申请日：2009-12-29

申请人： David P. Chengson ,  Chang-Hong Wu

发明人： David P. Chengson ,  Chang-Hong Wu

IPC分类号： G06F13/14 ,  G06F3/00 ,  G06F5/00 ,  G06F1/04 ,  G06F1/12 ,  G06F5/06

CPC分类号： G06F13/1689 ,  H04L25/03866 ,  H04L25/06

摘要： A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.

摘要翻译： 一个设备跨设备的第一个组件和第二个组件应用同步时钟，并从一组串行链路指定一个特定的串行链路作为主串行链路。 该设备还将剩余的串行链路指定为从串行链路，通过主串行链路提供编码数据流，并通过从串行链路提供未编码和加扰的数据流。

公开(公告)号：US08433905B2

公开(公告)日：2013-04-30

申请号：US12593334

申请日：2008-03-03

申请人： Kaoru Uchida ,  Akira Monden

发明人： Kaoru Uchida ,  Akira Monden

IPC分类号： G06F5/06 ,  G06F7/78

CPC分类号： H04L63/08

摘要： This invention provides a user authentication control device, a user authentication device, a data processing device, and a user authentication control method and the like that control an authentication interval and an authentication effective period in accordance with a communication speed so as to make it possible to keep a balance between user convenience and safety. The user authentication device, which controls an authentication effective period for a user authentication device of a data processing device connected with a server device through a network, is provided with a bandwidth acquiring unit for acquiring a communication speed of the network and an effective period determining unit for determining an authentication effective period in accordance with the communication speed.

摘要翻译： 本发明提供一种根据通信速度控制认证间隔和认证有效期的用户认证控制装置，用户认证装置，数据处理装置和用户认证控制方法等，以使其成为可能 以保持用户方便和安全之间的平衡。 用于通过网络控制与服务器装置连接的数据处理装置的用户认证装置的认证有效期的用户认证装置具有获取网络的通信速度的带宽取得部， 用于根据通信速度确定认证有效期的单元。

公开(公告)号：US08335941B2

公开(公告)日：2012-12-18

申请号：US12752201

申请日：2010-04-01

申请人： Nai-Shung Chang ,  Chia-Hsing Yu

发明人： Nai-Shung Chang ,  Chia-Hsing Yu

IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F5/06

CPC分类号： G06F1/324 ,  G06F1/3225 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.

摘要翻译： 提供了一种降低处于工作状态的计算机系统的功耗的方法。 计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。 该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电 通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。 当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

公开(公告)号：US08171334B2

公开(公告)日：2012-05-01

申请号：US12824463

申请日：2010-06-28

申请人： James D. Kelly

发明人： James D. Kelly

IPC分类号： G06F1/00 ,  G06F1/12 ,  G06F5/06

CPC分类号： G06F5/06

摘要： A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same clock frequency, typically one domain has a faster clock speed than the other. The gearbox is disposed between the two clock domains to control timing of data transfer from one to the other, by selecting a pattern which identifies when data is made transparent for the transfer. The gearbox allows a number of clock ratios to be selected, so that a particular clock ratio between the two domains may be readily selected in the gearbox for the data transfer.

摘要翻译： 齿轮箱放置在两个时钟域之间，以允许数据从一个域传输到另一个域。 尽管两个域可以在相同的时钟频率下工作，但通常一个域具有比另一个更快的时钟速度。 齿轮箱设置在两个时钟域之间，以通过选择识别数据何时使传输透明的模式来控制数据从一个到另一个的数据传输的定时。 齿轮箱允许选择多个时钟比，使得两个域之间的特定时钟比可以容易地在用于数据传输的变速箱中选择。