公开(公告)号：US5721563A

公开(公告)日：1998-02-24

申请号：US590578

申请日：1996-01-24

Applicant: Yuuichi Memida

Inventor： Yuuichi Memida

IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G11C27/02

CPC classification number: G09G3/3688 ,  G11C27/026 ,  G09G3/2011

Abstract: An active matrix liquid crystal drive circuit comprising an input-signal storage capacitor for storing an analog input signal, a differential amplifier which alternately presents a first operative state in which the output thereof is returned to the inverting input terminal thereof in a negative feedback manner and a second operative state in which the output is returned to the non-inverting input terminal thereof through a polarity inverting output buffer circuit in a negative feedback manner, and an output-voltage storage capacitor for storing an output voltage of the differential amplifier. In the first operative state, the voltage stored in the input-signal storage capacitor is applied to the non-inverting input terminal, and the output voltage which is returned to the inverting input terminal in a negative feedback manner is stored in the hold capacitor. In the second operative state, the voltage of the output-voltage storage capacitor is applied to the inverting input terminal and the output of the buffer circuit is output as a liquid crystal drive voltage.

Abstract translation: 一种有源矩阵液晶驱动电路，包括用于存储模拟输入信号的输入信号存储电容器，以负反馈方式交替呈现其输出返回其反相输入端的第一操作状态的差分放大器，以及 第二操作状态，其中输出通过极性反转输出缓冲电路以负反馈方式返回到其非反相输入端，以及输出电压存储电容器，用于存储差分放大器的输出电压。 在第一操作状态下，将存储在输入信号存储电容器中的电压施加到非反相输入端子，并且以负反馈方式返回到反相输入端子的输出电压被存储在保持电容器中。 在第二操作状态下，将输出电压存储电容器的电压施加到反相输入端子，并将缓冲电路的输出作为液晶驱动电压输出。

公开(公告)号：US5691657A

公开(公告)日：1997-11-25

申请号：US600007

申请日：1996-02-14

Applicant: Yoji Hirano ,  Goro Ueda

Inventor： Yoji Hirano ,  Goro Ueda

IPC: G11C27/02 ,  H03F3/04 ,  H03M1/12

CPC classification number: G11C27/026

Abstract: A sample-and-hold circuit comprises an analog signal control circuit for supplying a potential of an input signal to one end of a hold capacitor, a first transistor having a base connected to the one end of the hold capacitor and operating in an emitter follower fashion, an amplifier having a second transistor having a base connected to an emitter of the first transistor, and a leak current compensating circuit including a third transistor having an emitter connected to a collector of the first transistor and a current mirror circuit for supplying to the base of the first transistor the same current as a base current of the third transistor.

Abstract translation: 采样保持电路包括用于向保持电容器的一端提供输入信号的电位的模拟信号控制电路，第一晶体管，其基极连接到保持电容器的一端，并在发射极跟随器 具有第二晶体管的放大器，其具有连接到第一晶体管的发射极的基极，以及漏电流补偿电路，包括具有连接到第一晶体管的集电极的发射极的第三晶体管和用于向第一晶体管供电的电流镜电路 第一晶体管的基极与第三晶体管的基极电流相同的电流。

公开(公告)号：US5570048A

公开(公告)日：1996-10-29

申请号：US554399

申请日：1995-11-06

Applicant: Johannes J. F. Rijns

Inventor： Johannes J. F. Rijns

IPC: G11C27/02 ,  H03K17/16

CPC classification number: G11C27/026 ,  H03K17/162

Abstract: A sample-and-hold circuit comprises a first buffer stage, a first sampling switch, a sampling capacitor, and a feedback output amplifier for supplying a sampled output signal (Uout). The sampling capacitor is connected to an output of a second buffer stage, which has an input connected to earth. The output amplifier receives feedback via a third buffer stage and a second sampling switch and via a fourth buffer stage and a second sampling capacitor, which together with the first sampling switch are controlled by the same clock signal. The first sampling switch gives rise to clock feedthrough at the non-inverting input of the output amplifier. This clock feedthrough is cancelled by an equal clock feedthrough at the inverting input, so that the sampled output signal is freed from undesired clock feedthrough.

Abstract translation: 采样保持电路包括第一缓冲级，第一采样开关，采样电容器和用于提供采样输出信号（Uout）的反馈输出放大器。 采样电容器连接到具有连接到地的输入的第二缓冲级的输出端。 输出放大器经由第三缓冲级和第二采样开关以及经由第四缓冲级和第二采样电容器接收反馈，第一采样开关由第一采样开关由相同的时钟信号控制。 第一采样开关在输出放大器的非反相输入端产生时钟馈通。 这个时钟馈通在反相输入端通过相等的时钟馈通来消除，使得采样的输出信号免于不期望的时钟馈通。

公开(公告)号：US5554944A

公开(公告)日：1996-09-10

申请号：US496279

申请日：1995-06-28

Applicant: Marinus C. W. Van Buul ,  Petrus G. M. Centen

Inventor： Marinus C. W. Van Buul ,  Petrus G. M. Centen

IPC: G11C19/28 ,  G11C27/02

CPC classification number: G11C27/026

Abstract: In a sampling circuit including a first main terminal (P) and a series coupling of a hold capacitor (C2) and a sampling switch (S2) between the first main terminal (P) and a second main terminal (E), a parallel circuit (L2, R4) of a coil and a resistor (L2) is coupled in series with the sampling switch (S2) and the hold capacitor (C2), whereby the combination of the coil (L2), the resistor (R4) and the hold capacitor (C2) generate an excitation within a time period in which the sampling switch (S2) is conductive.

Abstract translation: 在包括第一主端子（P）和第一主端子（P）和第二主端子（E）之间的保持电容器（C2）和采样开关（S2）的串联耦合的采样电路中，并联电路 线圈（L2）和电阻器（L2）的组合与采样开关（S2）和保持电容器（C2）串联耦合，由此线圈（L2），电阻器（R4）和 保持电容器（C2）在采样开关（S2）导通的时间段内产生激励。

公开(公告)号：US5517141A

公开(公告)日：1996-05-14

申请号：US400686

申请日：1995-03-08

Applicant: Behrooz Abdi ,  Gary Stuhlmiller

Inventor： Behrooz Abdi ,  Gary Stuhlmiller

IPC: G11C27/02

CPC classification number: G11C27/026

Abstract: A differential track and hold amplifier circuit (200) is provided. The track and hold amplifier includes an input transconductance amplifier (212), an output amplifier (111), and a second transconductance amplifier (214). The track and hold circuit further includes a switching circuit (108) for coupling the output of the input transconductance amplifier to a capacitor (110) in the output stage of the track and hold circuit during track mode, and for decoupling the capacitor from the input amplifier during hold mode. The track and hold circuit further includes a subtractor circuit (103) for reducing a common mode voltage of the output of the input transconductance amplifier, thereby maintaining a stable voltage across the capacitor during hold mode. Further, during hold mode, the second transconductance amplifier acts in a negative feedback configuration to reduce the gain of the input amplifier to attenuate its output signal.

Abstract translation: 提供差分跟踪和保持放大器电路（200）。 轨道和保持放大器包括输入跨导放大器（212），输出放大器（111）和第二跨导放大器（214）。 轨道和保持电路还包括用于在轨道模式期间将输入跨导放大器的输出耦合到轨道和保持电路的输出级中的电容器（110）的开关电路（108），以及用于将电容器与输入端 放大器在保持模式下。 轨道和保持电路还包括用于减小输入跨导放大器的输出的共模电压的减法器电路（103），从而在保持模式期间保持电容器两端的稳定电压。 此外，在保持模式期间，第二跨导放大器作用在负反馈配置中以减小输入放大器的增益以衰减其输出信号。

公开(公告)号：US5510736A

公开(公告)日：1996-04-23

申请号：US278364

申请日：1994-07-21

Applicant: Rudy Van de Plassche

Inventor： Rudy Van de Plassche

IPC: G11C27/02

CPC classification number: G11C27/026

Abstract: The subject of the invention is a differential sampler circuit including a voltage/current converter (1) having two differential inputs (E1a, E1b) and two outputs (S1a, S1b). According to the invention, each of these outputs is linked via an input multiplexer module (2a) to two interposed track-and-hold modules (5a, 6a), in such a way that at any instant one of the track-and-hold modules (5a, 6a) operates in track mode whereas the other (6a, 5a) operates in hold mode. These two modules (5a, 6a) are linked to the output (S4a) of the sampler circuit via an output multiplexer module (7a). This structure makes it possible to double the sampling frequency without increasing the intrinsic speed of the circuit. Each track-and-hold module (5a, 6a) includes an input load (10a, 11a) linked in parallel with a capacitor (C18a, C19a), an output emitter-follower transistor (T20a, T21a), and a switching cell (5-6a). Thus, the high-frequency performance of the circuit is improved.

Abstract translation: 本发明的主题是包括具有两个差分输入（E1a，E1b）和两个输出（S1a，S1b）的电压/电流转换器（1）的差分采样器电路。 根据本发明，这些输出中的每一个通过输入多路复用器模块（2a）链接到两个插入的跟踪和保持模块（5a，6a），使得在任何时刻跟踪和保持模式 模块（5a，6a）以轨道模式工作，而另一个（6a，5a）工作在保持模式。 这两个模块（5a，6a）经由输出多路复用器模块（7a）链接到采样器电路的输出（S4a）。 这种结构使得可以使采样频率加倍而不增加电路的固有速度。 每个跟踪保持模块（5a，6a）包括与电容器（C18a，C19a）并联连接的输入负载（10a，11a），输出射极跟随器晶体管（T 20a，T21a）和开关单元 （5-6a）。 因此，提高了电路的高频性能。

公开(公告)号：US5467035A

公开(公告)日：1995-11-14

申请号：US315716

申请日：1994-09-30

Applicant: Susumu Ohi ,  Hiroshi Shiba

Inventor： Susumu Ohi ,  Hiroshi Shiba

IPC: G11C27/02 ,  H03K17/66 ,  H03K5/00

CPC classification number: H03K17/667 ,  G11C27/026

Abstract: An input terminal is connected to bases of first and second transistors. Collectors of the first and fourth transistors are connected to a power-source terminal. Collectors of the second and third transistors are grounded. A base of the third transistor is connected to an emitter of the first transistor. A base of the fourth transistor is connected to an emitter of the second transistor. One terminal of the capacitor is grounded and the other terminal thereof is connected to emitters of the third and fourth transistors and an input of an output buffer whose output is connected to an output terminal. A collector of a fifth transistor is connected to the power-source terminal and a base thereof is connected to the output terminal. A collector of a sixth transistor is grounded and a base thereof is connected to the output terminal. A first constant-current source is connected to an emitter of the fifth transistor and a base of the fourth transistor. A second constant-current source is connected to an emitter of the sixth transistor and the base of the third transistor. A third constant-current source is connected to the emitter of the first transistor and turned on at a sampling time. A fourth constant-current source is connected to the emitter of the second transistor and turned on at the sampling time.

Abstract translation: 输入端子连接到第一和第二晶体管的基极。 第一和第四晶体管的集电极连接到电源端子。 第二和第三晶体管的集电极接地。 第三晶体管的基极连接到第一晶体管的发射极。 第四晶体管的基极连接到第二晶体管的发射极。 电容器的一个端子接地，另一个端子连接到第三和第四晶体管的发射极，输出端连接到输出端子的输出缓冲器的输入端。 第五晶体管的集电极连接到电源端子，其基极连接到输出端子。 第六晶体管的集电极接地，其基极连接到输出端子。 第一恒流源连接到第五晶体管的发射极和第四晶体管的基极。 第二恒流源连接到第六晶体管的发射极和第三晶体管的基极。 第三恒流源连接到第一晶体管的发射极，并在采样时间导通。 第四恒流源连接到第二晶体管的发射极，并在采样时间导通。

公开(公告)号：US5341037A

公开(公告)日：1994-08-23

申请号：US886904

申请日：1992-05-22

Applicant: Takahiro Miki ,  Toshio Kumamoto

Inventor： Takahiro Miki ,  Toshio Kumamoto

IPC: G11C27/02 ,  H03K5/159

CPC classification number: G11C27/026 ,  G11C27/024

Abstract: Positive and negative output ends of a differential circuit in a sample hold circuit are connected to capacitors through switch circuits. Further, collectors of two input transistors of a buffer circuit connected to the sample hold circuit are driven by a collector driving differential circuit, so as to make the collector.multidot.base voltages of two input transistors same to each other. Consequently, a stable sample hold circuit having an arbitrary gain can be provided. In addition, drifts of outputs from two capacitors in the sample hold circuit can be made equal to each other by the buffer circuit.

Abstract translation: 采样保持电路中的差分电路的正和负输出端通过开关电路连接到电容器。 此外，连接到采样保持电路的缓冲电路的两个输入晶体管的集电极由集电极驱动差分电路驱动，以使两个输入晶体管的集电极基极彼此相同。 因此，可以提供具有任意增益的稳定的采样保持电路。 此外，可以通过缓冲电路将采样保持电路中的两个电容器的输出漂移相互相等。

公开(公告)号：US5339459A

公开(公告)日：1994-08-16

申请号：US985477

申请日：1992-12-03

Applicant: Thomas E. Schiltz ,  Carl R. Nuckolls

Inventor： Thomas E. Schiltz ,  Carl R. Nuckolls

IPC: G11C27/02 ,  H04B1/26 ,  H04B1/28 ,  H03K5/159

CPC classification number: H04B1/0014 ,  G11C27/026 ,  H04B1/0003 ,  H04B1/0025 ,  H04B1/0039 ,  H04B1/26

Abstract: A sample and hold circuit is formed within an integrated circuit and has a small, substantially linear hold capacitance. The circuit includes a sampling switch, a hold capacitor, and a buffer amplifier. The buffer amplifier includes a common drain FET and a constant current source FET. The common drain FET provides an input which couples to the hold capacitor. The constant current FET isolates the source of the common drain FET from ground. The sample and hold circuit may be used as a wide bandwidth mixer. In a radio application, a pulse generator provides a stream of pulses in which the sampling rate times an integer number equals the RF frequency minus the IF frequency. The width of the sampling pulse is less than the period of an RF signal. In an oscillator application, the sample and hold circuit operates as a mixer in a frequency multiplying phase locked loop.

Abstract translation: 采样和保持电路形成在集成电路内并且具有小的，基本上线性的保持电容。 电路包括采样开关，保持电容和缓冲放大器。 缓冲放大器包括公共漏极FET和恒流源FET。 公共漏极FET提供耦合到保持电容的输入。 恒流FET将公共漏极FET的源极与地相隔离。 采样和保持电路可以用作宽带混频器。 在无线电应用中，脉冲发生器提供脉冲流，其中采样率乘以整数等于RF频率减去IF频率。 采样脉冲的宽度小于RF信号的周期。 在振荡器应用中，采样和保持电路在倍频锁相环中作为混频器工作。

公开(公告)号：US5315169A

公开(公告)日：1994-05-24

申请号：US894980

申请日：1992-06-08

Applicant: Lloyd F. Linder ,  Benjamin Felder ,  Dwight D. Birdsall

Inventor： Lloyd F. Linder ,  Benjamin Felder ,  Dwight D. Birdsall

IPC: G11C27/02 ,  H03F3/50 ,  H03F3/72 ,  H03K17/00 ,  H03K17/74 ,  H03K5/24

CPC classification number: H03F3/50 ,  G11C27/026 ,  H03F3/72 ,  H03K17/74 ,  H03K2217/0036

Abstract: A diode bridge includes a plurality of diodes for coupling an input voltage signal to a holding capacitor for sampling when the diodes are forward biased, and uncoupling the voltage signal from the capacitor for holding when the diodes are reverse biased. The diode bridge has first and second bias current nodes. A constant current drain causes a constant bias current to flow out of the bridge. A transistor connects the first node to the drain for forward biasing the diodes, whereas a transistor connects the second node to the drain for reverse biasing the diodes. A bootstrap amplifier (A2) produces a variable control voltage which controls a pair of voltage-controlled constant current sources to cause the constant bias current to flow therethrough into the bridge. A transistor (Q7) couples the control voltage to the first current source for forward biasing the diodes, whereas a transistor couples the control voltage to the second current source for reverse biasing the diodes. The transistors are all bipolar and of the same conductivity type, preferably NPN.

Abstract translation: 二极管桥包括多个二极管，用于将输入电压信号耦合到保持电容器，用于当二极管正向偏置时进行采样，以及当二极管反向偏置时，将来自电容器的电压信号与电容器断开耦合以进行保持。 二极管桥具有第一和第二偏置电流节点。 恒流漏极导致恒定的偏置电流流出桥。 晶体管将第一节点连接到漏极，用于正向偏置二极管，而晶体管将第二节点连接到漏极，以反向偏置二极管。 自举放大器（A2）产生可变控制电压，其控制一对电压控制的恒流源，以使恒定的偏置电流流过其中。 晶体管（Q7）将控制电压耦合到第一电流源以用于正向偏置二极管，而晶体管将控制电压耦合到第二电流源以反向偏置二极管。 晶体管都是双极型的，具有相同的导电类型，最好是NPN。