公开(公告)号：US11626359B2

公开(公告)日：2023-04-11

申请号：US17242083

申请日：2021-04-27

Applicant: QUALCOMM Incorporated

Inventor： Biancun Xie ,  Shree Krishna Pandey ,  Irfan Khan ,  Miguel Miranda Corbalan ,  Stanley Seungchul Song

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/065

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.

公开(公告)号：US11545555B2

公开(公告)日：2023-01-03

申请号：US16944624

申请日：2020-07-31

Applicant: QUALCOMM Incorporated

Inventor： Peijie Feng ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L29/423 ,  H01L29/167 ,  H01L29/78 ,  H01L29/06

Abstract: Gate-all-around (GAA) transistors with shallow source/drain regions and methods of fabricating the same provide a GAA transistor that includes one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire, nanosheet, or nanoslab semiconductors, are surrounded along a longitudinal axis by gate material. At a first end of the channel is a source region and at an opposite end of the channel is a drain region. To reduce parasitic capacitance between a bottom gate and the source and drain regions, a filler material is provided adjacent the bottom gate, and the source and drain regions are grown on top of the filler material. In this fashion, the bottom gate does not abut the source region or the drain region, reducing geometries which would contribute to parasitic capacitance.

公开(公告)号：US11302638B2

公开(公告)日：2022-04-12

申请号：US16738127

申请日：2020-01-09

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/535

Abstract: Certain aspects of the present disclosure generally relate to integration of a hybrid conductor material in power rails of a semiconductor device. An example semiconductor device generally includes an active electrical device and a power rail. The power rail is electrically coupled to the active electrical device, disposed above the active electrical device, and embedded in at least one dielectric layer. The power rail includes a first conductive layer, a barrier layer, and a second conductive layer. In certain cases, copper may be used as conductive material for the second conductive layer. The barrier layer is disposed between the first conductive layer and the second conductive layer.

公开(公告)号：US20220102266A1

公开(公告)日：2022-03-31

申请号：US17038098

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin Lim ,  Stanley Seungchul Song ,  Foua Vang ,  Seung Hyuk Kang

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods are disclosed. The circuit includes a front side metal line disposed adjacent to a front side of a semiconductor device for providing front side signal routing. The circuit also includes a back side metal line disposed adjacent to a back side of the semiconductor device for providing back side signal routing. In this manner, the back side area of the semiconductor device may be employed for signal routing to conserve area and/or reduce routing complexity. The circuit also includes a back side-front side connection structure that electrically couples the front side metal line to the back side metal line to support signal routing from the back side to the front side of the circuit, or vice versa to provide greater routing flexibility.

公开(公告)号：US11270991B1

公开(公告)日：2022-03-08

申请号：US17010001

申请日：2020-09-02

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Stanley Seungchul Song ,  Mohammed Yousuff Shariff

IPC: H01L27/06 ,  H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48

Abstract: Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS)) BEOL (BS-BEOL) power routing for current flow organization, and related IC packages and methods of fabricating are disclosed. The IC includes a FS-BEOL metallization structure disposed on a first side of a semiconductor layer and a BS-BEOL metallization structure disposed on a second side of the semiconductor layer. The FS-BEOL metallization structure is configured to route I/O signals to the semiconductor devices. The FS-BEOL metallization structure of the IC is also configured to receive power signals to be routed to the semiconductor devices. However, to avoid the need to route the power signals to semiconductor devices through the FS-BEOL metallization structure, thus increasing routing density and complexity the FS-BEOL metallization structure, the power signals are routed from the FS-BEOL metallization structure to the BS-BEOL metallization structure and to semiconductor devices for power.

公开(公告)号：US11195793B2

公开(公告)日：2021-12-07

申请号：US16743350

申请日：2020-01-15

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Stanley Seungchul Song

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/535 ,  H01L23/528

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for fabricating a semiconductor device. A semiconductor device includes: an active device layer a local interconnect layer disposed above the active device layer; a dielectric layer disposed above the local interconnect layer; a metal layer disposed above the dielectric layer; and one or more metal sections disposed in the dielectric layer underneath one or more metal regions of the metal layer, wherein none of the one or more metal sections is electrically connected to a trace in the local interconnect layer.

公开(公告)号：US10700204B2

公开(公告)日：2020-06-30

申请号：US16104522

申请日：2018-08-17

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Da Yang ,  Peijie Feng

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/165

Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

公开(公告)号：US10418244B2

公开(公告)日：2019-09-17

申请号：US15408796

申请日：2017-01-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Giridhar Nallapati ,  Periannan Chidambaram

IPC: H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L21/033 ,  G03F7/00 ,  H01L21/308 ,  H01L27/118

Abstract: Aspects describing modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area are disclosed. In one aspect, a modified SAQP process includes disposing multiple mandrels. First spacers are disposed on either side of each mandrel, and second spacers are disposed on either side of each first spacer. A cut pattern mask is disposed over the second spacers and includes openings that expose second spacers corresponding to locations in which voltage rails are to be disposed. The voltage rails are formed by removing the second spacers exposed by the openings in the cut pattern mask, and disposing the voltage rails in the corresponding locations left vacant by removing the second spacers. Routing lines are disposed over routing tracks formed between each set of the remaining second spacers to allow for interconnecting of active devices formed in the IC cell.

公开(公告)号：US20190195700A1

公开(公告)日：2019-06-27

申请号：US16268669

申请日：2019-02-06

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  Periannan Chidambaram ,  Bin Yang ,  Jiefeng Jeff Lin ,  Giridhar Nallapati ,  Bo Yu ,  Jie Deng ,  Jun Yuan ,  Stanley Seungchul Song

IPC: G01K7/01 ,  H01L23/522 ,  H01L23/34 ,  G01K7/18 ,  H01L49/02 ,  G01K7/24 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/528 ,  H01L21/66

CPC classification number: G01K7/01 ,  G01K7/186 ,  G01K7/24 ,  H01L21/32139 ,  H01L21/76895 ,  H01L22/34 ,  H01L23/34 ,  H01L23/5228 ,  H01L23/528 ,  H01L27/0629 ,  H01L28/24

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

公开(公告)号：US20190067435A1

公开(公告)日：2019-02-28

申请号：US16171061

申请日：2018-10-25

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L29/49 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78

Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.