公开(公告)号：US20010004328A1

公开(公告)日：2001-06-21

申请号：US09736121

申请日：2000-12-15

Applicant: TRIXELL S.A.S.

Inventor： Thierry Ducourant

IPC: G11C005/00

CPC classification number: G11C27/026

Abstract: A circuit for the reading of charges injected at its input comprises a read MOS transistor, the type of which conditions the polarity of the charges that the read circuit is capable of reading without getting blocked, and an integration capacitor mounted between a first electrode of the drain-source pair of the read MOS transistor and a reference potential. The input of the circuit is at the second electrode of the drain-source pair of the read MOS transistor. The injected charges must cross the read MOS transistor to be integrated by the capacitor. The read MOS transistor is controlled by a control voltage that varies in a manner that is substantially inversely proportional to the input voltage. The circuit has means to detect the arrival, at the input, of charges with a polarity opposite to the polarity of the charges that it is capable of reading and means for the imposing, on the input voltage, after a detection of this kind, of an equilibrium value equal or close to a basic value that it takes between two successive operations of integrating charges with the desired polarity so as to prevent a prolonged blocking of the read MOS transistor at the arrival of charges with a desired polarity

Abstract translation: 用于读取在其输入处注入的电荷的电路包括读取MOS晶体管，其类型决定了读取电路能够读取而不被阻塞的电荷的极性，以及集成电容器，安装在第一电极 读取MOS晶体管的漏 - 源对和参考电位。 电路的输入位于读取MOS晶体管的漏 - 源对的第二电极。 注入的电荷必须穿过读取的MOS晶体管才能被电容器集成。 读出的MOS晶体管是以与输入电压基本上成反比的方式变化的控制电压来控制的。 该电路具有在这种检测之后，在输入端检测与输入电压相反极性与其能够读取的电荷极性相反的电荷到达输入电压的装置的装置， 平衡值等于或接近基本值，该基本值在两个相继的操作之间积分所需的极性电荷，以防止在所需极性的电荷到达时读取的MOS晶体管被长期阻塞

公开(公告)号：US06232804B1

公开(公告)日：2001-05-15

申请号：US09413751

申请日：1999-10-06

Applicant: Takeshi Shigenobu ,  Masao Ito ,  Toshio Kumamoto

Inventor： Takeshi Shigenobu ,  Masao Ito ,  Toshio Kumamoto

IPC: G11C2702

CPC classification number: G11C27/026

Abstract: In a sample hold circuit (6, 50, 60) capable of relaxing a dependency of a voltage of an analogue input signal on an ON resistance of a switch (2). In the sample hold circuit (6, 50, 60), plural reference voltages VrefN are supplied, and unit switches (11e) forming the switch (2) are selectively activated (an ON state) based on a comparison results (whether or not the voltage of the analogue input signal is greater than each reference voltage) from plural comparison circuits (13e) whose operations are performed based on the voltage of the analogue input signal (1).

Abstract translation: 在能够放松模拟输入信号的电压对开关（2）的导通电阻的依赖性的采样保持电路（6,50,60）中。 在采样保持电路（6,50,60）中，提供多个参考电压VrefN，并且基于比较结果（形成开关（2））的单元开关（11e）是否被选择性地激活（ON状态） 根据模拟输入信号（1）的电压执行其操作的多个比较电路（13e），模拟输入信号的电压大于每个参考电压）。

公开(公告)号：US6060914A

公开(公告)日：2000-05-09

申请号：US131778

申请日：1998-08-10

Applicant: Hideo Nunokawa

Inventor： Hideo Nunokawa

IPC: H01L21/8238 ,  G05F3/24 ,  G11C27/02 ,  H01L27/092 ,  H03K17/06 ,  H03M1/12

CPC classification number: G11C27/026 ,  H03K17/063

Abstract: A semiconductor device includes a sample and hold circuit which has an analog switch and a first capacitor and which samples and holds an analog input signal, and a boost circuit which has a boost part which boosts a sampling clock pulse and a clamp part which limits a boosted voltage to a predetermined level. The sample and hold circuit operates a boosted sampling clock pulse. The boost circuit includes a control circuit which operates the clamp part only at the moment the sampling clock pulse changes to a high level.

Abstract translation: 半导体器件包括具有模拟开关和第一电容器并且采样并保持模拟输入信号的采样和保持电路，以及升压电路，其具有提升采样时钟脉冲的升压部分和限制采样时钟脉冲的钳位部分 升压至预定电平。 采样和保持电路操作升压的采样时钟脉冲。 升压电路包括仅在采样时钟脉冲变为高电平时操作钳位部分的控制电路。

公开(公告)号：US06034556A

公开(公告)日：2000-03-07

申请号：US19363

申请日：1998-02-05

Applicant: Takahisa Koyasu ,  Mitsuhiro Saitou ,  Hiroyuki Ban

Inventor： Takahisa Koyasu ,  Mitsuhiro Saitou ,  Hiroyuki Ban

IPC: G11C27/02 ,  H03F3/30 ,  H03F3/45

CPC classification number: H03F3/3071 ,  G11C27/026 ,  H03F3/45085 ,  H03F2203/45594 ,  H03F2203/45612 ,  H03F2203/45618 ,  H03F2203/45674 ,  H03F2203/45722

Abstract: An operational amplifier charges a charge storage capacitor in response to an input signal supplied to a non-inverting input terminal. When a switching signal is low, NPN transistors disposed in an output open circuit are on. Therefore, output transistors disposed in a push-pull circuit are off and the output signal is cut off. Further, in this situation, the potential of a phase compensation capacitor is held because AC coupling of the phase compensation capacitor does not occur.

Abstract translation: 响应于提供给非反相输入端的输入信号，运算放大器对电荷存储电容器充电。 当开关信号为低电平时，设置在输出开路中的NPN晶体管导通。 因此，设置在推挽电路中的输出晶体管截止，输出信号被切断。 此外，在这种情况下，由于不发生相位补偿电容器的AC耦合，因此保持相位补偿电容器的电位。

公开(公告)号：US5994928A

公开(公告)日：1999-11-30

申请号：US83221

申请日：1998-05-22

Applicant: Gilles Chevallier

Inventor： Gilles Chevallier

IPC: G11C27/02 ,  H03M1/12

CPC classification number: G11C27/026

Abstract: A comparator (22) compares the output signal (Vout) supplied by an output amplifier (21) with an input signal (Vin). Dependent on the result of the comparison, it controls the conduction of one or the other of two sources (IGA, IGB) which supply opposite currents. Two complementary assemblies (A, B) each comprise a first transistor (T1A, T1B) and a second transistor (T2A, T2B). Each first transistor (T1A, T1B) has its base controlled by one of the current sources for charging a first capacitance (C1) connected to the output, and also controls the conduction of the corresponding second transistor. The bases of the second transistors (T2A, T2B) are jointly connected to the first capacitance (C1) and their emitters are jointly connected to the negative input of the output amplifier (21). The negative input of the output amplifier (21) is also connected to a reference voltage (Vref) via a resistor (20) and to the output (Vout) via a second capacitance (C2).

Abstract translation: 比较器（22）将由输出放大器（21）提供的输出信号（Vout）与输入信号（Vin）进行比较。 取决于比较的结果，它控制提供相反电流的两个源（IGA，IGB）中的一个或另一个的导通。 两个互补组件（A，B）各自包括第一晶体管（T1A，T1B）和第二晶体管（T2A，T2B）。 每个第一晶体管（T1A，T1B）的基极由一个电流源控制，用于对连接到输出端的第一电容（C1）充电，并且还控制对应的第二晶体管的导通。 第二晶体管（T2A，T2B）的基极共同连接到第一电容（C1），它们的发射极共同连接到输出放大器（21）的负输入端。 输出放大器（21）的负输入也经由电阻（20）连接到参考电压（Vref），经由第二电容（C2）连接到输出（Vout）。

公开(公告)号：US5982205A

公开(公告)日：1999-11-09

申请号：US953551

申请日：1997-10-17

Applicant: David Gerard Vallancourt

Inventor： David Gerard Vallancourt

IPC: G11C27/02 ,  H03M1/12

CPC classification number: G11C27/026

Abstract: A very low voltage sampling circuit which is capable of a full ranging output when powered with a very low voltage, e.g., of about 1 volt. A pre-charge circuit is combined with a sample and hold circuit to avoid the need for low threshold switching devices in the sampling circuit, thus avoiding output droop due to the increased leakage of low threshold devices. The pre-charge circuit is placed between the sample and hold circuit and an output of the sampling circuit to `boost` the voltage level of the output of the sample and hold circuit to above a predetermined threshold voltage level. The pre-charge circuit includes an output voltage boost capacitor which is charged before the hold cycle of the sampling circuit. The negative node of the output voltage boost capacitor is charged to a reference voltage, and the positive node is charged approximately to a level of the input signal itself.

Abstract translation: 一种非常低电压的采样电路，当以非常低的电压（例如约1伏特）供电时，能够进行全范围输出。 预充电电路与采样和保持电路组合以避免对采样电路中的低阈值开关器件的需要，从而避免了由于低阈值器件的泄漏增加引起的输出下降。 预充电电路放置在采样保持电路和采样电路的输出之间，以将采样和保持电路的输出的电压电平“升高”到高于预定阈值电压电平。 预充电电路包括在采样电路的保持周期之前充电的输出升压电容器。 输出升压电容器的负极被充电到参考电压，正极节点约为输入信号本身的电平。

公开(公告)号：US5914638A

公开(公告)日：1999-06-22

申请号：US870498

申请日：1997-06-06

Applicant: Xinping He

Inventor： Xinping He

IPC: G11C27/02 ,  H03F3/00 ,  H03F3/45

CPC classification number: G11C27/026 ,  H03F3/005 ,  H03F3/45753 ,  H03F3/45977

Abstract: A fully differential sample-and-hold amplifier 60 includes a common-mode feedback circuit 100 for adjusting the common-mode input so that the common-mode output remains near a desired level. During a first switching state, the sample-and-hold amplifier samples voltages and is coupled to the feedback circuit 100 for the adjustment of the common-mode input level. During a second switching state, sample-and-hold amplifier performs its charge transfer and amplification function while the feedback circuit 100 is not coupled to the sample-and-hold amplifier. During the first switching state, the feedback circuit 100 receives as an input the common-mode voltage of the operational amplifier and outputs an amplification of the difference between the common-mode voltage and a regulating input voltage. The output of the sample-and-hold amplifier is coupled to the common-mode input of the operational amplifier. In this manner, differences between the common-mode voltage of the operational amplifier and the regulating voltage are used to adjust the common-mode input of the operational amplifier so that the common-mode output of the operational amplifier approximates the regulating voltage. The common-mode feedback circuit 100 includes a current source I1, a pair of differential input transistors M3 and M4, and a pair of load transistors M1 and M2. The gate of the input transistor M3 is coupled to the regulating voltage, while the gate of the input transistor M4 is coupled by a switching means to the output of the operational amplifier. The load transistors M1 and M2 are connected in an active load configuration. The output of the common-mode feedback circuit 100 is taken from the drain of the load transistor M1. The operational amplifier used in the sample-and-hold amplifier may be a telescopic cascode operational transconductance amplifier.

Abstract translation: 全差分采样和保持放大器60包括用于调整共模输入的共模反馈电路100，使得共模输出保持在期望的水平附近。 在第一开关状态期间，采样和保持放大器对电压进行采样并耦合到反馈电路100以调整共模输入电平。 在第二开关状态期间，采样和保持放大器执行其电荷转移和放大功能，而反馈电路100未耦合到采样和保持放大器。 在第一开关状态期间，反馈电路100接收运算放大器的共模电压作为输入，并输出共模电压和调节输入电压之间的差的放大。 采样保持放大器的输出端耦合到运算放大器的共模输入端。 以这种方式，使用运算放大器的共模电压与调节电压之间的差异来调节运算放大器的共模输入，使得运算放大器的共模输出接近调节电压。 共模反馈电路100包括电流源I1，一对差分输入晶体管M3和M4以及一对负载晶体管M1和M2。 输入晶体管M3的栅极耦合到调节电压，而输入晶体管M4的栅极通过开关装置耦合到运算放大器的输出端。 负载晶体管M1和M2以有源负载配置连接。 共模反馈电路100的输出从负载晶体管M1的漏极取出。 采样保持放大器中使用的运算放大器可以是伸缩共源共栅工作跨导放大器。

公开(公告)号：US5851864A

公开(公告)日：1998-12-22

申请号：US956074

申请日：1997-10-22

Applicant: Akira Ito ,  Michael David Church

Inventor： Akira Ito ,  Michael David Church

IPC: G05F3/30 ,  G11C27/02 ,  H01L21/8249 ,  H01L27/02 ,  H01L27/06 ,  H03F1/52 ,  H03F3/50 ,  H03G1/00 ,  H03K5/15 ,  H03K17/22 ,  H03M1/16 ,  H03M1/36 ,  H01L7/44

CPC classification number: H03K5/15 ,  G05F3/30 ,  G11C27/026 ,  H01L21/8249 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0688 ,  H03F1/523 ,  H03F3/505 ,  H03G1/0082 ,  H03K17/223 ,  H03M1/162 ,  H03F2200/294 ,  H03M1/365

Abstract: A BiCMOS process which provides both low voltage (digital) and high voltage (analog) CMOS devices. The high voltage NMOS devices have a compensated drain formed by the NPN and PNP base implants. The PNP base plus the high voltage NMOS drain carrier concentrations are both optimized by adjustment of the two variables N base implant dose and P base implant dose; this determines the NPN base carrier concentration which turns out to provide good NPN characteristics. Low voltage NMOS source and drain implants employ a higher dose and may also be used for the high voltage NMOS source. The NPN emitter doping may also be used for a contact to the high voltage NMOS drain contact.

Abstract translation: 提供低电压（数字）和高电压（模拟）CMOS器件的BiCMOS工艺。 高压NMOS器件具有由NPN和PNP基极植入物形成的补偿漏极。 PNP基极加上高压NMOS漏极载流子浓度都通过调整两个变量N基础植入剂量和P基础植入剂量进行优化; 这确定了NPN基载波浓度，证明其具有良好的NPN特性。 低电压NMOS源极和漏极注入采用更高的剂量，也可用于高电压NMOS源。 NPN发射极掺杂也可用于与高压NMOS漏极接触的接触。

公开(公告)号：US5838175A

公开(公告)日：1998-11-17

申请号：US795222

申请日：1997-02-05

Applicant: Kuo-Chiang Hsieh

Inventor： Kuo-Chiang Hsieh

IPC: G11C27/02

CPC classification number: G11C27/026

Abstract: A low distortion track-and-hold circuit in which a simple, four-transistor amplifier makes the circuit characteristics independent of the source impedance, and compensates for unequal voltage drops caused by mismatched diodes. An additional pair of bipolar transistors is used to eliminate errors caused by switching transients coupled through the diodes. In the track mode, the differential output voltage between two sampling capacitors tracks the differential input voltage of the circuit. At the end of the track time, this differential output voltage is equal to the differential input voltage. During the hold period, the sampling capacitors are isolated from the differential input voltage. The voltages controlling the switching diodes reverse symmetrically during the transition from track to hold, resulting in a cancellation of any feedthrough of the switching transients to the sampling capacitor. Beta and temperature compensation circuits are also included in the differential track-and-hold circuit. In a single-ended in and single-ended out configuration, an operational amplifier can be used to provide a unity-gain buffer and the correct voltage offset. The invention may be implemented using bipolar transistors, MOSFET and JFET technologies.

Abstract translation: 低失真跟踪保持电路，其中简单的四晶体管放大器使得电路特性与源阻抗无关，并且补偿由不匹配的二极管引起的不相等的电压降。 另外一对双极性晶体管被用于消除通过二极管耦合的开关瞬变引起的误差。 在轨道模式下，两个采样电容之间的差分输出电压跟踪电路的差分输入电压。 在跟踪时间结束时，该差分输出电压等于差分输入电压。 在保持期间，采样电容与差分输入电压隔离。 在从轨道转换到保持期间，控制开关二极管的电压对称地反向，导致对采样电容器的开关瞬变的任何馈通的消除。 差分跟踪保持电路中还包括Beta和温度补偿电路。 在单端和单端输出配置中，运算放大器可用于提供单位增益缓冲器和正确的电压偏移。 本发明可以使用双极晶体管，MOSFET和JFET技术来实现。

公开(公告)号：US5774181A

公开(公告)日：1998-06-30

申请号：US872653

申请日：1997-06-10

Applicant: Tai-Ching Shyu ,  Datong Chen

Inventor： Tai-Ching Shyu ,  Datong Chen

IPC: G11C27/02 ,  H03F1/30 ,  H03K5/24 ,  H04N5/357 ,  H04N5/374 ,  H04N5/378 ,  H04N5/335

CPC classification number: H03K5/249 ,  G11C27/026 ,  H03F1/303 ,  H04N5/3658 ,  H04N5/374 ,  H04N5/378

Abstract: A charge amplifier with DC offset cancelling for use in a pixel element of an MOS image sensor is disclosed. The charge amplifier can be manufactured using a standard CMOS single polycrystalline process, making it much more cost effective than prior art designs. The charge amplifier includes an operational amplifier, a source capacitor, a series capacitor, and a feedback capacitor. The source capacitor holds the input signal. The output of the operational amplifier provides the output signal. Switches control the routing of the signal flow from the source capacitor, the series capacitor, and the feedback capacitor.

Abstract translation: 公开了一种用于MOS图像传感器的像素元件的DC偏移消除的电荷放大器。 电荷放大器可以使用标准CMOS单晶多晶工艺制造，使其比现有技术设计更成本有效。 电荷放大器包括运算放大器，源极电容器，串联电容器和反馈电容器。 源极电容保持输入信号。 运算放大器的输出提供输出信号。 开关控制源电容，串联电容和反馈电容的信号流的路由。