公开(公告)号：US20210359096A1

公开(公告)日：2021-11-18

申请号：US16942310

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/28

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type work function metal; a barrier material over the first p-type work function metal; and a second p-type work function metal over the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal.

公开(公告)号：US20210313419A1

公开(公告)日：2021-10-07

申请号：US16842066

申请日：2020-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02

Abstract: A semiconductor device including a barrier layer surrounding a work function metal layer and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a second channel region over the first channel region; gate dielectric layers surrounding the first channel region and the second channel region; work function metal layers surrounding the gate dielectric layers; and barrier layers surrounding the work function metal layers, a first barrier layer surrounding the first channel region being merged with a second barrier layer surrounding the second channel region.

公开(公告)号：US20210233817A1

公开(公告)日：2021-07-29

申请号：US16870485

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L21/8234 ,  C23C16/34 ,  C23C16/455 ,  H01L21/285 ,  H01L21/28 ,  H01L21/764 ,  H01L29/66 ,  H01L27/088 ,  H01L29/08 ,  H01L29/06 ,  H01L29/49 ,  H01L29/45 ,  H01L29/417

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. After the recessing, a portion of a semiconductor material between the isolation region protrudes higher than top surfaces of the isolation regions to form a semiconductor fin. The method further includes forming a gate stack, which includes forming a gate dielectric on sidewalls and a top surface of the semiconductor fin, and depositing a titanium nitride layer over the gate dielectric as a work-function layer. The titanium nitride layer is deposited at a temperature in a range between about 300° C. and about 400° C. A source region and a drain region are formed on opposing sides of the gate stack.

公开(公告)号：US20210217870A1

公开(公告)日：2021-07-15

申请号：US16741767

申请日：2020-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi-On Chui

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/285 ,  H01L27/092

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate strip disposed over the substrate. The gate strip includes a high-k layer disposed over the substrate, an N-type work function metal layer disposed over the high-k layer, and a barrier layer disposed over the N-type work function metal layer. The barrier layer includes at least one first film containing TiAlN, TaAlN or AlN.

公开(公告)号：US10923576B2

公开(公告)日：2021-02-16

申请号：US16751128

申请日：2020-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Yen Tsai ,  Da-Yuan Lee

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/285 ,  H01L27/088 ,  H01L21/67 ,  H01L29/51

Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.

公开(公告)号：US10510621B2

公开(公告)日：2019-12-17

申请号：US15952534

申请日：2018-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zoe Chen ,  Ching-Hwanq Su ,  Cheng-Lung Hung ,  Cheng-Yen Tsai ,  Da-Yuan Lee ,  Hsin-Yi Lee ,  Weng Chang ,  Wei-Chin Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10

Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.

公开(公告)号：US20190318967A1

公开(公告)日：2019-10-17

申请号：US15952534

申请日：2018-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zoe Chen ,  Ching-Hwanq Su ,  Cheng-Lung Hung ,  Cheng-Yen Tsai ,  Da-Yuan Lee ,  Hsin-Yi Lee ,  Weng Chang ,  Wei-Chin Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10

Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.

公开(公告)号：US12283613B2

公开(公告)日：2025-04-22

申请号：US18418678

申请日：2024-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/40 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. The gate electrode includes a first work function metal; a second work function metal over the first work function metal; and a first metal residue at an interface between the first work function metal and the second work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal.

公开(公告)号：US20240387690A1

公开(公告)日：2024-11-21

申请号：US18786469

申请日：2024-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Chi On Chui

IPC: H01L29/66 ,  C23C18/16 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

Abstract: Embodiments utilize an electro-chemical process to deposit a metal gate electrode in a gate opening in a gate replacement process for a nanosheet FinFET device. Accelerators and suppressors may be used to achieve a bottom-up deposition for a fill material of the metal gate electrode.

公开(公告)号：US20240387672A1

公开(公告)日：2024-11-21

申请号：US18786531

申请日：2024-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/51 ,  H01L29/786

Abstract: Embodiments include a device and method of forming a device, such as a nano-FET transistor, including a first nanostructure. A gate dielectric is formed around the first nanostructure. A gate electrode is formed over the gate dielectric, and the gate electrode includes a first work function metal. In the gate electrode, a first metal residue is formed at an interface between the gate dielectric and the first work function metal as a result of a treatment process performed prior to forming the first work function metal. The first metal residue has a metal element that is different than a metal element of the first work function metal.