公开(公告)号：US20240258166A1

公开(公告)日：2024-08-01

申请号：US18608673

申请日：2024-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

公开(公告)号：US20240213157A1

公开(公告)日：2024-06-27

申请号：US18600197

申请日：2024-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L21/324 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/324 ,  H01L21/76876 ,  H01L23/5226

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

公开(公告)号：US12009202B2

公开(公告)日：2024-06-11

申请号：US17379161

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan Lee ,  Hsin-Yen Huang ,  Yung-Hsu Wu ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/48 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/02304 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226

Abstract: A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

公开(公告)号：US20240085803A1

公开(公告)日：2024-03-14

申请号：US18514254

申请日：2023-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Hsiang-Wei Liu ,  Shau-Lin Shue ,  Li-Lin Su ,  Yung-Hsu Wu

IPC: G03F7/00 ,  G03F7/004 ,  G03F7/09 ,  H01L21/768

CPC classification number: G03F7/70633 ,  G03F7/0035 ,  G03F7/0043 ,  G03F7/0047 ,  G03F7/094 ,  G03F7/70625 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/76849

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

公开(公告)号：US11710700B2

公开(公告)日：2023-07-25

申请号：US17391216

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Yu-Chen Chan ,  Ming-Han Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53276 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53295

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature.

公开(公告)号：US11640924B2

公开(公告)日：2023-05-02

申请号：US17314877

申请日：2021-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Yu-Chieh Liao ,  Chia-Tien Wu ,  Hsin-Ping Chen ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/532 ,  H01L23/522 ,  H01L21/3105

Abstract: The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer.

公开(公告)号：US20230118565A1

公开(公告)日：2023-04-20

申请号：US18066464

申请日：2022-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768

Abstract: The present disclosure provides a method that includes depositing a metal layer onto a substrate, subtractive patterning the metal layer into first metal lines, and forming at least one second metal line between two adjacent ones of the first metal lines using a damascene process. The first metal lines have a different metallization structure from the at least one second metal line.

公开(公告)号：US11450602B2

公开(公告)日：2022-09-20

申请号：US16837762

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768

Abstract: The present disclosure provides a method for forming semiconductor structures. The method includes providing a device having a substrate, a first dielectric layer over the substrate, and a first conductive feature over the first dielectric layer, the first conductive feature comprising a first metal, the first metal being a noble metal. The method also includes depositing a second dielectric layer over the first dielectric layer and covering at least sidewalls of the first conductive feature; etching the second dielectric layer to form a trench; and forming a second conductive feature in the trench. The second conductive feature comprises a second metal different from the first metal.

公开(公告)号：US20220157711A1

公开(公告)日：2022-05-19

申请号：US17097505

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan Lee ,  Hsin-Yen Huang ,  Cheng-Chin Lee ,  Kuang-Wei Yang ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L21/768

Abstract: The present disclosure relates an integrated chip. The integrated chip may include a first interconnect and a second interconnect disposed within a first inter-level dielectric (ILD) layer over a substrate. A lower etch stop structure is disposed on the first ILD layer and a third interconnect is disposed within a second ILD layer that is over the first ILD layer. The third interconnect extends through the lower etch stop structure to contact the first interconnect. An interconnect patterning layer is disposed on the second interconnect and laterally adjacent to the lower etch stop structure.

公开(公告)号：US20220157690A1

公开(公告)日：2022-05-19

申请号：US17097441

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan Lee ,  Cherng-Shiaw Tsai ,  Ting-Ya Lo ,  Cheng-Chin Lee ,  Chi-Lin Teng ,  Kai-Fang Cheng ,  Hsin-Yen Huang ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC: H01L23/373 ,  H01L23/48 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.