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5586 条记录 (耗时 0.038 秒)

    Low-power block code forward error correction decoder
    91.
    发明授权
    Low-power block code forward error correction decoder 有权

    公开(公告)号：US11750223B2

    公开(公告)日：2023-09-05

    申请号：US16367538

    申请日：2019-03-28

    申请人： Maxlinear, Inc.

    发明人： Youzhe Fan ,  Jining Duan

    IPC分类号： H03M13/15 ,  H03M13/00 ,  H03M13/11

    CPC分类号： H03M13/1545 ,  H03M13/1105 ,  H03M13/157 ,  H03M13/6561

    摘要： A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.

    Error correction method, error correction circuit and electronic device applying the same
    93.
    发明授权
    Error correction method, error correction circuit and electronic device applying the same 有权

    公开(公告)号：US11736121B1

    公开(公告)日：2023-08-22

    申请号：US17827029

    申请日：2022-05-27

    申请人： ETRON TECHNOLOGY, INC.

    发明人： Ho-Yin Chen ,  Han-Hsien Wang ,  Han-Nung Yeh

    IPC分类号： H03M13/09 ,  H03M13/00 ,  H03M13/11

    CPC分类号： H03M13/098 ,  H03M13/1108 ,  H03M13/6597

    摘要： An error correction method comprises: when a decoder determines that an input analog code is at a forbidden state, setting a digital binary code as a first predetermined code and inputting the digital binary code to an ECC engine; determining whether the digital binary code has no error or two errors; when the digital binary code has no error, outputting the digital binary code after ECC by the ECC engine; when the digital binary code has two errors, resetting the digital binary code as a second predetermined code and inputting the digital binary code to the ECC engine for ECC; and when the decoder determines that the input analog code is not at the forbidden state, decoding the input analog code into the digital binary code and inputting the digital binary code to the ECC engine for ECC.

    Bit flipping low-density parity-check decoders with low error floor
    96.
    发明授权
    Bit flipping low-density parity-check decoders with low error floor 有权

    公开(公告)号：US11711095B2

    公开(公告)日：2023-07-25

    申请号：US17729775

    申请日：2022-04-26

    申请人： Micron Technology, Inc.

    发明人： Mustafa N. Kaynak ,  Sivagnanam Parthasarathy

    IPC分类号： H03M13/00 ,  H03M13/11 ,  H03M13/29 ,  H03M13/15

    CPC分类号： H03M13/1108 ,  H03M13/1177 ,  H03M13/1575 ,  H03M13/2948

    摘要： A memory device having a Low-Density Parity-Check (LDPC) decoder that is energy efficient and has a low error floor. The decoder is configured to determine syndromes of bits in a codeword, select bits in the codeword based at least in part on the syndromes according to a first mode, and flip the selected bits in the codeword. The decoder can repeat the bit selection and flipping operations to iteratively improve the codeword and reduce parity violations. Further, the decoder can detect a pattern in parity violations of the codeword in its iterative bit flipping operations. In response, the decoder can change from the first mode to a second mode in bit selection for flipping. For example, the decoder can transmit from a dynamic syndrome mode to a static syndrome mode in response to the pattern of repeating a cycle of bit flipping iterations.

    ITERATIVE ERROR CORRECTION IN MEMORY SYSTEMS
    97.
    发明公开
    ITERATIVE ERROR CORRECTION IN MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20230231573A1

    公开(公告)日：2023-07-20

    申请号：US17843171

    申请日：2022-06-17

    申请人： Micron Technology, Inc.

    发明人： Marco SFORZIN ,  DI HSIEN NGU

    IPC分类号： H03M13/09 ,  H03M13/11 ,  H03K19/173

    CPC分类号： H03M13/098 ,  H03M13/1174 ,  H03M13/1171 ,  H03K19/1737

    摘要： A system and method for detecting and correcting memory errors in CXL components is presented. The method includes receiving, into a decoder, a memory transfer block (MTB), wherein the MTB comprises data and parity information, wherein the MTB is arranged in a first dimension and a second dimension. An error checking and a correction function on the MTB is performed using a binary hamming code logic within the decoder in the first dimension. An error checking and a correction function on the MTB is performed using a non-binary hamming code logic within the decoder in the second dimension. Further, the binary hamming code logic and the non-binary hamming code logic perform the error checking on the MTB simultaneously.

    ARTIFICIAL INTELLIGENCE AUGMENTED ITERATIVE PRODUCT DECODING
    100.
    发明公开
    ARTIFICIAL INTELLIGENCE AUGMENTED ITERATIVE PRODUCT DECODING 审中-公开

    公开(公告)号：US20230216522A1

    公开(公告)日：2023-07-06

    申请号：US18091605

    申请日：2022-12-30

    申请人： QUANTUM CORPORATION

    发明人： Suayb S. Arslan ,  Turguy Goker

    IPC分类号： H03M13/11

    CPC分类号： H03M13/1105

    摘要： A method for product decoding within a data storage system includes receiving data to be decoded within a first decoder; performing a plurality of decoding iterations to decode the data utilizing a first decoder and a second decoder; and outputting fully decoded data based on the performance of the plurality of decoding iterations. Each of the plurality of decoding iterations includes (i) decoding the data with the first decoder operating at a first decoder operational mode to generate once decoded data; (ii) sending the once decoded data from the first decoder to the second decoder; (iii) receiving error information from the first decoder with an artificial intelligence system; (iv) selecting a second decoder operational mode based at least in part on the error information that is received by the artificial intelligence system; and (v) decoding the once decoded data with the second decoder operating at the second decoder operational mode to generate twice decoded data; and outputting fully decoded data based on the performance of the plurality of decoding iterations.