公开(公告)号：US20070205482A1

公开(公告)日：2007-09-06

申请号：US11364953

申请日：2006-03-01

Applicant: Chih-Chao Yang ,  Terry Spooner ,  Oscar Straten

Inventor： Chih-Chao Yang ,  Terry Spooner ,  Oscar Straten

IPC: H01L29/00

CPC classification number: H01L21/76831 ,  H01L21/02063 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/32131 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the overlying line opening, nor does it introduce damages caused by Ar sputtering into the dielectric material including the via and line openings. In accordance with the present invention, such an interconnect structure contains a diffusion barrier layer only within the via opening, but not in the overlying line opening. This feature enhances both mechanical strength and diffusion property around the via opening areas without decreasing volume fraction of conductor inside the line openings. In accordance with the present invention, such an interconnect structure is achieved by providing the gouging feature in the bottom of the via opening prior to formation of the line opening and deposition of the diffusion barrier in said line opening.

Abstract translation: 提供一种互连结构，其包括在一个通孔开口的底部的气泡特征及其形成方法。 根据本发明，形成互连结构的方法不会破坏上覆线路开口中沉积的扩散阻挡层的覆盖，也不会引起由Ar溅射引起的包括通孔和线路开口的电介质材料的损伤。 根据本发明，这种互连结构仅在通孔开口内包含扩散阻挡层，但不包括在上覆开口中。 该特征增强了通孔开口区域周围的机械强度和扩散性能，而不会降低线路开口内导体的体积分数。 根据本发明，这种互连结构是通过在形成线路开口和在所述线路开口中的扩散阻挡层的沉积之前提供通孔开口的底部中的气流特征来实现的。

公开(公告)号：US20070197033A1

公开(公告)日：2007-08-23

申请号：US11358659

申请日：2006-02-21

Applicant: Aaron Wilson

Inventor： Aaron Wilson

IPC: C23F1/00 ,  H01L21/302

CPC classification number: H01L21/31116 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/31138

Abstract: A process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by supplying a first gaseous etchant having at least fifty (50) percent He to a plasma etch reactor, and exposing the insulating layer to a plasma of the first gaseous etchant. Use of the first gaseous etchant reduces the occurrence of twisting in openings in insulating layers having an aspect ratio of at least 15:1.

Abstract translation: 通过向等离子体蚀刻反应器提供具有至少五十（50）％的He的第一气态蚀刻剂，并且将绝缘层暴露于等离子体中，蚀刻绝缘层以产生纵横比为至少15:1的开口的方法 的第一种气体蚀刻剂。 使用第一种气体蚀刻剂减少了具有至少15:1的纵横比的绝缘层中的开口扭曲的发生。

公开(公告)号：US07037848B2

公开(公告)日：2006-05-02

申请号：US10871291

申请日：2004-06-17

Applicant: Daryl C. New

Inventor： Daryl C. New

IPC: H01L21/302

CPC classification number: H01L28/55 ,  H01L21/31105 ,  H01L21/31122 ,  H01L21/32131 ,  H01L21/32136

Abstract: In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In another aspect, the invention encompasses a method of forming a capacitor. An electrically conductive first layer is formed over a substrate, and a second layer is formed over the first layer. The second layer is a dielectric layer and comprises a complex of metal and oxygen. A conductive third layer is formed over the second layer. The first, second and third layers are patterned into a capacitor construction. The patterning of the second layer comprises exposing the second layer to at least one oxygen-containing gas while also exposing the second layer to physical etching conditions.

公开(公告)号：US06902987B1

公开(公告)日：2005-06-07

申请号：US09505283

申请日：2000-02-16

Applicant: Qin-Yi Tong ,  Gaius Gillman Fountain, Jr. ,  Paul M. Enquist

Inventor： Qin-Yi Tong ,  Gaius Gillman Fountain, Jr. ,  Paul M. Enquist

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/20 ,  H01L21/58 ,  H01L21/48

CPC classification number: H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process the method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

Abstract translation: 在低温或室温下接合的方法包括通过清洗或蚀刻进行表面清洁和活化的步骤。 一种蚀刻工艺，该方法还可以包括除去界面聚合的副产物以防止反向聚合反应，以允许诸如硅，氮化硅和SiO 2的材料的室温化学键合。 要结合的表面被抛光到高度的平滑度和平坦度。 VSE可以使用反应离子蚀刻或湿蚀刻来稍微蚀刻被结合的表面。 表面粗糙度和平面度不会降低，并且可以通过VSE工艺增强。 蚀刻的表面可以在诸如氢氧化铵或氟化铵的溶液中冲洗以促进在表面上形成所需的粘结物质。

公开(公告)号：US20050079712A1

公开(公告)日：2005-04-14

申请号：US10913441

申请日：2004-08-09

Applicant: Qin-Yi Tong ,  Gaius Fountain ,  Paul Enquist

Inventor： Qin-Yi Tong ,  Gaius Fountain ,  Paul Enquist

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/20 ,  H01L21/58 ,  H01L21/30 ,  H01L21/302 ,  H01L21/46 ,  H01L21/461

CPC classification number: H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

Abstract translation: 在低温或室温下接合的方法包括通过清洗或蚀刻进行表面清洁和活化的步骤。 一种蚀刻方法该方法还可以包括除去界面聚合的副产物以防止反向聚合反应，以允许诸如硅，氮化硅和SiO 2的材料的室温化学键合。 要结合的表面被抛光到高度的平滑度和平坦度。 VSE可以使用反应离子蚀刻或湿蚀刻来稍微蚀刻被结合的表面。 表面粗糙度和平面度不会降低，并且可以通过VSE工艺增强。 蚀刻的表面可以在诸如氢氧化铵或氟化铵的溶液中冲洗以促进在表面上形成所需的粘结物质。

公开(公告)号：US06878639B1

公开(公告)日：2005-04-12

申请号：US10667013

申请日：2003-09-19

Applicant: Ming-Huan Tsai ,  Ru-Chian Chiang ,  Hun-Jan Tao

Inventor： Ming-Huan Tsai ,  Ru-Chian Chiang ,  Hun-Jan Tao

IPC: H01L21/302 ,  H01L21/311 ,  H01L21/60

CPC classification number: H01L21/76897 ,  H01L21/31105 ,  H01L21/31116

Abstract: A new method for fabricating a borderless interconnection in a semiconductor device is provided. During fabrication, the device includes an interlevel dielectric (ILD) layer, a metal silicide layer, and a stop layer disposed between the ILD and metal silicide layers. The stop layer may be formed of silicon nitride or silicon oxynitride, and the metal silicide layer may be a nickel silicide. The method includes etching the ILD layer to expose at least a portion of the stop layer and then performing a nitrogen plasma treatment on the exposed portion of the stop layer. After the treatment, the exposed portion of the stop layer is removed to provide the interconnection hole. Because of the plasma treatment, damage to the metal silicide underlying the stop layer will be minimized when the stop layer is removed.

Abstract translation: 提供了一种在半导体器件中制造无边界互连的新方法。 在制造期间，器件包括层间电介质（ILD）层，金属硅化物层和设置在ILD和金属硅化物层之间的阻挡层。 阻挡层可以由氮化硅或氮氧化硅形成，并且金属硅化物层可以是硅化镍。 该方法包括蚀刻ILD层以暴露停止层的至少一部分，然后在停止层的暴露部分上进行氮等离子体处理。 在处理之后，去除停止层的暴露部分以提供互连孔。 由于等离子体处理，当停止层被去除时，对停止层下面的金属硅化物的损坏将被最小化。

公开(公告)号：US06815326B2

公开(公告)日：2004-11-09

申请号：US10391197

申请日：2003-03-19

Applicant: Kouichi Asai ,  Kazutoshi Sakai ,  Kazuya Suzuki ,  Hirofumi Koike ,  Shunji Yoshikane ,  Kenji Tanaka

Inventor： Kouichi Asai ,  Kazutoshi Sakai ,  Kazuya Suzuki ,  Hirofumi Koike ,  Shunji Yoshikane ,  Kenji Tanaka

IPC: H01L2144

CPC classification number: H01L21/31105 ,  H01L21/283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object of the present invention is to provide a technique for forming an ohmic connection between a semiconductor and a metal efficiently in a short period of time. The present invention provides a method of forming at least one electrode on a surface of a semiconductor, wherein a metal or alloy for the electrode is rubbed against a predetermined region of the semiconductor surface so as to be adhered by frictional force and frictional heat to the predetermined region of the semiconductor as an electrode and part of the adhered metal or a metal of the alloy is diffused into an inside of the semiconductor by the frictional heat thereby to be formed into an ohmic electrode substantially simultaneously when the metal or alloy is adhered by the frictional force and frictional heat to the predetermined region of the semiconductor.

Abstract translation: 本发明的目的是提供一种在短时间内有效地形成半导体与金属之间的欧姆连接的技术。本发明提供一种在半导体的表面上形成至少一个电极的方法，其中 用于电极的金属或合金被摩擦到半导体表面的预定区域，以便通过摩擦力和摩擦热粘附到半导体的预定区域作为电极和部分粘附的金属或合金的金属 通过摩擦热扩散到半导体的内部，从而当通过摩擦力和摩擦热将金属或合金粘附到半导体的预定区域时，基本上同时形成欧姆电极。

公开(公告)号：US20040147100A1

公开(公告)日：2004-07-29

申请号：US10760905

申请日：2004-01-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY

Inventor： Syun-Ming Jang ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L021/20

CPC classification number: H01L21/76832 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/31127 ,  H01L21/31138 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/76807

Abstract: A method for forming within a substrate employed within a microelectronics fabrication a damascene multi-layer conductor interconnection layer with inhibited/attenuated damage to a conductor stud layer accessed therein within a trench, when forming the trench interconnection pattern within a dielectric layer overlying the conductor stud layer. There is provided a substrate having a contact region formed therein employing a first intermediate metal dielectric (IMD) layer having a pattern of via contact holes etched through the IMD layer filled with studs of conductor material. There is then planarized the surface of the IMD contact region. There is then formed over the planarized first IMD layer contact region a blanket composite etch stop layer. There is the formed over the blanket composite etch stop layer a second blanket inter-level metal dielectric (IMD) layer. A patterned photoresist etch mask layer formed into the interconnection trench pattern is then formed over the substrate and employed to transfer the trench pattern into the second IMD layer and the upper sub-layer of the composite etch stop layer. The interconnection trench pattern is then transferred by a second subtractive etch into the lower sub-layer of the composite etch stop layer, employing the second IMD layer as an etch mask A barrier metal layer is then formed over the substrate. The trench pattern is then filled with a second conductor material to complete the damascene multi-layer conductor interconnection layer, with improved electrical conductivity and contact properties and inhibited/attenuated degradation effects due to processing on the damascene interconnection layer.

Abstract translation: 一种用于在微电子学制造中使用的衬底内形成的镶嵌多层导体互连层的方法，其在沟槽内存在于其中的导体柱层的受损/衰减损伤时，当在覆盖导体柱的电介质层内形成沟槽互连图案时 层。 提供了一种其中形成有接触区域的基板，其中采用第一中间金属电介质（IMD）层，其具有通过填充有导体材料柱的IMD层蚀刻的通孔接触孔的图案。 然后平面化IMD接触区域的表面。 然后在平坦化的第一IMD层接触区域上形成覆盖复合蚀刻停止层。 在覆盖层复合蚀刻停止层上形成第二毯层级金属电介质（IMD）层。 形成在互连沟槽图案中的图案化的光致抗蚀剂蚀刻掩模层然后形成在衬底上并用于将沟槽图案转移到复合蚀刻停止层的第二IMD层和上部子层中。 然后通过第二减法蚀刻将互连沟槽图案转移到复合蚀刻停止层的下部子层中，采用第二IMD层作为蚀刻掩模。然后在衬底上形成阻挡金属层。 然后用第二导体材料填充沟槽图案以完成镶嵌多层导体互连层，具有改善的导电性和接触性能以及由于在镶嵌互连层上的加工而被抑制/减弱的降解效应。

公开(公告)号：US06707114B1

公开(公告)日：2004-03-16

申请号：US10321250

申请日：2002-12-16

Applicant: Charles E. May ,  Hemanshu Bhatt

Inventor： Charles E. May ,  Hemanshu Bhatt

IPC: H01L2976

CPC classification number: H01L21/76897 ,  H01L21/31105 ,  H01L29/6656

Abstract: A method of processing a semiconductor wafer and an associated semiconductor wafer arrangement which inhibits “punch through” and increases the yield of functional semiconductor wafers during the fabrication thereof is disclosed.

Abstract translation: 公开了一种处理半导体晶片和相关半导体晶片布置的方法，该方法在其制造期间抑制“穿透”并增加功能半导体晶片的产量。

公开(公告)号：US20030224601A1

公开(公告)日：2003-12-04

申请号：US10160606

申请日：2002-05-30

Inventor： Erwan Le Roy ,  Mark A. Thompson

IPC: H01L021/302 ,  H01L021/461 ,  H01L021/311

CPC classification number: H01J37/3005 ,  H01J37/228 ,  H01J37/3056 ,  H01J2237/2482 ,  H01J2237/30455 ,  H01J2237/31737 ,  H01J2237/3174 ,  H01J2237/31744 ,  H01L21/2633 ,  H01L21/26506 ,  H01L21/3065 ,  H01L21/31105

Abstract: Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using an FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The floor of the trench is formed so as to be as smooth and planar as possible, thereby preventing undesirable exposure of the underlying active regions through any unknown or undesired cavity caused by scratches or pits or a deeper than desired sidewall. The smoothness and planarity of the floor of the trench is established by, prior to forming the trench, removing any surface defect initially present by using an FIB etching without use of assist gas to eliminate most scratches or impurities on the surface of the silicon, followed by removal of implanted ions using a gas-injected assisted FIB etch. Then the actual trench is formed using an assisted etch using a more aggressive injected gas.

Abstract translation: 用于从集成电路衬底的背面暴露诸如金属化层的选定部分的集成电路器件的选定特征的装置和方法，而不干扰诸如有源半导体区域的器件的相邻特征。 这是通过FIB（聚焦离子束）蚀刻工艺结合光学显微镜的观察来进行的，以通过衬底形成沟槽。 沟槽的底部形成为尽可能平坦和平坦，从而防止潜在的有源区域通过由划痕或凹坑或更深于期望的侧壁引起的任何未知或不期望的空腔的不希望的暴露。 通过在形成沟槽之前，通过使用FIB蚀刻而不使用辅助气体来除去最初存在的任何表面缺陷，以消除硅表面上的大多数划痕或杂质，建立沟槽底板的平滑度和平坦度，随后 通过使用气体注入的辅助FIB蚀刻去除注入的离子。 然后使用更积极的注入气体的辅助蚀刻形成实际沟槽。