公开(公告)号：US09773533B2

公开(公告)日：2017-09-26

申请号：US14297645

申请日：2014-06-06

申请人： Etron Technology, Inc.

发明人： Chun Shiah

IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C8/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/4091 ,  G11C8/18 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/408 ,  G11C8/12

CPC分类号： G11C7/12 ,  G11C7/06 ,  G11C8/08 ,  G11C8/12 ,  G11C8/18 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/2281 ,  G11C2207/229

摘要： A method for reducing current consumption of a memory is disclosed, wherein the memory includes a controller and a plurality of banks, and each bank of the plurality of banks includes a plurality of segments. The method includes the controller enabling an activating command corresponding to a first row address and an address of a first bank of the plurality of banks; a word line switch of a segment of the first bank corresponding to the first row address being turned on according to the activating command; the controller enabling an access command corresponding to an address of the segment; a plurality of bit switches corresponding to the segment being turned on according to the access command; and the controller enabling a pre-charge command corresponding to an address of a following segment and the address of the first bank after the access command is disabled.

公开(公告)号：US09666247B2

公开(公告)日：2017-05-30

申请号：US15156919

申请日：2016-05-17

申请人： SK hynix Inc.

发明人： Chang Yong Ahn ,  Ho Seok Em

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C7/12 ,  G11C13/00 ,  G11C16/10 ,  G11C16/34 ,  G11C11/16

CPC分类号： G11C7/062 ,  G11C7/1063 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/3459 ,  G11C2013/0042 ,  G11C2207/229

摘要： A semiconductor memory apparatus may include a write driver, a data sensing section, and a programming control section. The write driver may write an input data into a memory cell in response to a write signal. The data sensing section may generate a comparison flag signal by comparing an output data outputted from the memory cell with a reference voltage in response to a verification read signal. The programming control section may generate the write signal for an initial write operation and the verification read signal as soon as the comparison flag signal is enabled.

公开(公告)号：US20170109308A1

公开(公告)日：2017-04-20

申请号：US15395598

申请日：2016-12-30

申请人： SK hynix Inc.

发明人： Kyung-Whan KIM ,  Dong-Uk LEE

IPC分类号： G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G11C7/22 ,  G11C8/18

CPC分类号： G11C7/1006 ,  G06F13/161 ,  G06F13/4027 ,  G06F13/4286 ,  G11C7/1018 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C2207/005 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.

公开(公告)号：US20170097904A1

公开(公告)日：2017-04-06

申请号：US15314316

申请日：2015-05-26

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Craig E. Hampel

IPC分类号： G06F13/16 ,  G11C11/4093 ,  G11C11/408 ,  G06F13/40

CPC分类号： G06F13/1673 ,  G06F13/4068 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1042 ,  G11C11/4082 ,  G11C11/4093 ,  G11C2207/229

摘要： A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.

公开(公告)号：US09368171B2

公开(公告)日：2016-06-14

申请号：US14562936

申请日：2014-12-08

申请人： SK hynix Inc.

发明人： Chang Yong Ahn ,  Ho Seok Em

IPC分类号： G11C7/22 ,  G11C7/06 ,  G11C7/12

CPC分类号： G11C7/062 ,  G11C7/1063 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/3459 ,  G11C2013/0042 ,  G11C2207/229

摘要： A semiconductor memory apparatus may include a write driver, a data sensing section, and a programming control section. The write driver may write an input data into a memory cell in response to a write signal. The data sensing section may generate a comparison flag signal by comparing an output data outputted from the memory cell with a reference voltage in response to a verification read signal. The programming control section may generate the write signal for an initial write operation and the verification read signal in response to a write command, and generate the write signal for a following write operation as soon as the comparison flag signal is at a predetermined level.

摘要翻译： 半导体存储装置可以包括写入驱动器，数据感测部分和编程控制部分。 写入驱动器可以响应写入信号将输入数据写入存储器单元。 数据检测部分可以通过响应于验证读取信号将从存储器单元输出的输出数据与参考电压进行比较来生成比较标志信号。 编程控制部分可以响应写入命令产生用于初始写入操作的写入信号和验证读取信号，并且一旦比较标志信号处于预定电平就产生用于后续写入操作的写入信号。

公开(公告)号：US20160078908A1

公开(公告)日：2016-03-17

申请号：US14948692

申请日：2015-11-23

申请人： SK hynix Inc.

发明人： Jung Hyuk YOON

IPC分类号： G11C7/06 ,  G11C8/10 ,  G11C8/06 ,  G11C5/14

CPC分类号： G11C8/06 ,  G11C5/14 ,  G11C7/22 ,  G11C8/10 ,  G11C13/0002 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2207/229

摘要： A semiconductor memory apparatus includes a command processing block configured to generate a voltage generation start signal, a first write control signal, a second write control signal, a read signal, and an operation signal in response to a first control signal and a second control signal in a write operation, and a memory control block configured to electrically couple a memory block, which stores data, to a sense amplifier or apply a predetermined voltage to the memory block in response to the voltage generation start signal, the first write control signal, the second write control signal, the read signal, and the operation signal.

摘要翻译： 半导体存储装置包括：命令处理块，其被配置为响应于第一控制信号和第二控制信号产生电压产生开始信号，第一写入控制信号，第二写入控制信号，读取信号和操作信号 以及存储器控制块，被配置为将存储数据的存储块电耦合到读出放大器或响应于电压产生开始信号向存储块施加预定电压，第一写入控制信号， 第二写入控制信号，读取信号和操作信号。

公开(公告)号：US20160064051A1

公开(公告)日：2016-03-03

申请号：US14562936

申请日：2014-12-08

申请人： SK hynix Inc.

发明人： Chang Yong AHN ,  Ho Seok EM

IPC分类号： G11C7/22 ,  G11C7/12 ,  G11C7/06

CPC分类号： G11C7/062 ,  G11C7/1063 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/3459 ,  G11C2013/0042 ,  G11C2207/229

摘要： A semiconductor memory apparatus may include a write driver, a data sensing section, and a programming control section. The write driver may write an input data into a memory cell in response to a write signal. The data sensing section may generate a comparison flag signal by comparing an output data outputted from the memory cell with a reference voltage in response to a verification read signal. The programming control section may generate the write signal for an initial write operation and the verification read signal in response to a write command, and generate the write signal for a following write operation as soon as the comparison flag signal is at a predetermined level.

摘要翻译： 半导体存储装置可以包括写入驱动器，数据感测部分和编程控制部分。 写入驱动器可以响应写入信号将输入数据写入存储器单元。 数据检测部分可以通过响应于验证读取信号将从存储器单元输出的输出数据与参考电压进行比较来生成比较标志信号。 编程控制部分可以响应写入命令产生用于初始写入操作的写入信号和验证读取信号，并且一旦比较标志信号处于预定电平就产生用于后续写入操作的写入信号。

公开(公告)号：US09037806B2

公开(公告)日：2015-05-19

申请号：US13790354

申请日：2013-03-08

申请人： International Business Machines Corporation

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F9/38 ,  G11C7/22

CPC分类号： G06F12/0806 ,  G06F9/38 ,  G06F9/3855 ,  G06F12/0855 ,  G11C7/22 ,  G11C2207/229 ,  Y02D10/13

摘要： A computer product for reducing store operation busy times is provided. The computer product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes associating first and second platform registers with a cache array, determining that first and second store operations target a same wordline of the cache array, loading control information and data of the first and second store operation into the first and second platform registers and delaying a commit of the first store operation until the loading of the second platform register is complete. The method further includes committing the data from the first and second platform registers using the control information from the first and second platform registers to the wordline of the cache array at a same time to thereby reduce a busy time of the wordline of the cache array.

摘要翻译： 提供了一种用于减少存储操作繁忙时间的计算机产品。 计算机产品包括可由处理电路读取的有形存储介质，并存储由处理电路执行以执行方法的指令。 该方法包括将第一和第二平台寄存器与高速缓存阵列相关联，确定第一和第二存储操作针对高速缓存阵列的相同字线，将控制信息和第一和第二存储操作的数据加载到第一和第二平台寄存器中，以及 延迟第一个存储操作的提交，直到第二个平台寄存器的加载完成。 该方法还包括使用来自第一和第二平台寄存器的控制信息将来自第一和第二平台寄存器的数据同时提交到高速缓存阵列的字线，从而减少高速缓存阵列的字线的繁忙时间。

公开(公告)号：US09015423B2

公开(公告)日：2015-04-21

申请号：US13523567

申请日：2012-06-14

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F9/38 ,  G11C7/22

CPC分类号： G06F12/0806 ,  G06F9/38 ,  G06F9/3855 ,  G06F12/0855 ,  G11C7/22 ,  G11C2207/229 ,  Y02D10/13

摘要： A computer product for reducing store operation busy times is provided and relates to associating first and second platform registers with a cache array, determining that first and second store operations target a same wordline of the cache array, loading control information and data of the store operations into the platform registers and delaying a commit of the first store operation until the loading of the second platform register is complete. The method further includes committing the data from the platform registers using the control information from the platform registers to the wordline of the cache array at a same time to thereby reduce a busy time of the wordline of the cache array.

摘要翻译： 提供了用于减少存储操作繁忙时间的计算机产品，并且涉及将第一和第二平台寄存器与高速缓存阵列相关联，确定第一和第二存储操作针对高速缓存阵列的相同字线，加载控制信息和存储操作的数据 进入平台寄存器并延迟第一个存储操作的提交，直到第二个平台寄存器的加载完成。 该方法还包括使用来自平台寄存器的控制信息将来自平台寄存器的数据同时提交到高速缓存阵列的字线，从而减少高速缓存阵列的字线的繁忙时间。

公开(公告)号：US08817555B2

公开(公告)日：2014-08-26

申请号：US13478727

申请日：2012-05-23

申请人： Sung-Hwa Ok

发明人： Sung-Hwa Ok

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/229

摘要： A semiconductor memory device includes an internal signal generation unit configured to output a column select signal and a write enable signal in response to an external address, a write circuit unit configured to output internal data corresponding to external data in response to the write enable signal, a core unit configured to store the internal data in response to the column select signal, and an output timing control unit configured to control output timings of the internal signal generation unit and the write circuit unit in response to an external command, an internal synchronization signal, and preamble related information.

摘要翻译： 半导体存储器件包括：内部信号生成单元，被配置为响应于外部地址输出列选择信号和写使能信号;写电路单元，被配置为响应于写使能信号输出与外部数据对应的内部数据， 核心单元，被配置为响应于列选择信号来存储内部数据;以及输出定时控制单元，被配置为响应于外部命令来控制内部信号生成单元和写入电路单元的输出定时，内部同步信号 和前导码相关信息。