公开(公告)号：US08058913B2

公开(公告)日：2011-11-15

申请号：US12392495

申请日：2009-02-25

申请人： Chulwoo Kim ,  Ja Bum Koo ,  Sung Hwa Ok

发明人： Chulwoo Kim ,  Ja Bum Koo ,  Sung Hwa Ok

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03K5/133 ,  H03K5/1565 ,  H03K2005/00026

摘要： The present invention relates to a delay-locked loop-based multiphase clock generator that generates a plurality of multiphase clocks from an input clock signal using a voltage controlled delay line including a plurality of dummy cells. The delay-locked loop-based multiphase clock generator includes an anti-harmonic lock circuit that receives an input clock and a reference clock of multiple clocks, determines whether a pulse signal derived from the input clock is within a normal locking range of the reference clock, and outputs a compulsory control signal to compulsorily control an output signal of a phase detector if it is determined that the pulse signal is not within the normal locking range.

摘要翻译： 本发明涉及一种基于延迟锁定环的多相时钟发生器，其使用包括多个虚拟单元的压控延迟线从输入时钟信号产生多个多相时钟。 基于延迟锁定环的多相时钟发生器包括接收输入时钟和多个时钟的参考时钟的反谐波锁定电路，确定从输入时钟导出的脉冲信号是否在参考时钟的正常锁定范围内 并且如果确定脉冲信号不在正常锁定范围内，则输出强制控制信号来强制地控制相位检测器的输出信号。

公开(公告)号：US08502577B2

公开(公告)日：2013-08-06

申请号：US12970913

申请日：2010-12-16

申请人： Sung Hwa Ok

发明人： Sung Hwa Ok

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0805

摘要： Various exemplary embodiments of a phase correction circuit are disclosed. In one exemplary embodiment, the phase correction circuit may include a delay unit configured to delay a clock signal by a predetermined delay time and generate a delay clock signal, a delay line configured to delay a data strobe signal by a variable delay time in response to a delay control signal and generate a corrected data strobe signal, a phase detector configured to detect a phase difference between the delay clock signal and the corrected data strobe signal and generate a phase detection signal, and a shift register configured to generate the delay control signal in response to the phase detection signal.

摘要翻译： 公开了相位校正电路的各种示例性实施例。 在一个示例性实施例中，相位校正电路可以包括延迟单元，其被配置为将时钟信号延迟预定延迟时间并产生延迟时钟信号，延迟线被配置为响应于可变延迟时间延迟数据选通信号 延迟控制信号并产生校正数据选通信号;相位检测器，被配置为检测延迟时钟信号和校正数据选通信号之间的相位差，并产生相位检测信号;以及移位寄存器，被配置为产生延迟控制信号 响应于相位检测信号。

公开(公告)号：US08441871B2

公开(公告)日：2013-05-14

申请号：US12980677

申请日：2010-12-29

申请人： Sung-Hwa Ok

发明人： Sung-Hwa Ok

IPC分类号： G11C7/00

CPC分类号： G11C7/1093 ,  G11C7/1084 ,  G11C2207/2272

摘要： A circuit for a semiconductor memory device includes: a filtering control signal generation unit configured to synchronize a seed signal activated in a pre-amble period of a data strobe signal with the data strobe signal and sequentially generate a plurality of filtering control signals in response to the seed signal; and a filtering signal output unit configured to generate a filtering signal for filtering the data strobe signal in response to the plurality of filtering control signals and a plurality of burst length (BL) control signals.

摘要翻译： 一种用于半导体存储器件的电路包括：滤波控制信号生成单元，被配置为使数据选通信号的前置时段中激活的种子信号与数据选通信号同步，并响应于 种子信号; 以及滤波信号输出单元，被配置为响应于所述多个滤波控制信号和多个突发长度（BL）控制信号而产生用于对数据选通信号进行滤波的滤波信号。

公开(公告)号：US20120106275A1

公开(公告)日：2012-05-03

申请号：US12980677

申请日：2010-12-29

申请人： Sung-Hwa OK

发明人： Sung-Hwa OK

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/1093 ,  G11C7/1084 ,  G11C2207/2272

摘要： A circuit for a semiconductor memory device includes: a filtering control signal generation unit configured to synchronize a seed signal activated in a pre-amble period of a data strobe signal with the data strobe signal and sequentially generate a plurality of filtering control signals in response to the seed signal; and a filtering signal output unit configured to generate a filtering signal for filtering the data strobe signal in response to the plurality of filtering control signals and a plurality of burst length (BL) control signals.

摘要翻译： 一种用于半导体存储器件的电路包括：滤波控制信号生成单元，被配置为使数据选通信号的前置时段中激活的种子信号与数据选通信号同步，并响应于 种子信号; 以及滤波信号输出单元，被配置为响应于所述多个滤波控制信号和多个突发长度（BL）控制信号而产生用于对数据选通信号进行滤波的滤波信号。

公开(公告)号：US20100013530A1

公开(公告)日：2010-01-21

申请号：US12392495

申请日：2009-02-25

申请人： Chulwoo Kim ,  Ja Bum Koo ,  Sung Hwa Ok

发明人： Chulwoo Kim ,  Ja Bum Koo ,  Sung Hwa Ok

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03K5/133 ,  H03K5/1565 ,  H03K2005/00026

摘要： The present invention relates to a delay-locked loop-based multiphase clock generator that generates a plurality of multiphase clocks from an input clock signal using a voltage controlled delay line including a plurality of dummy cells. The delay-locked loop-based multiphase clock generator includes an anti-harmonic lock circuit that receives an input clock and a reference clock of multiple clocks, determines whether a pulse signal derived from the input clock is within a normal locking range of the reference clock, and outputs a compulsory control signal to compulsorily control an output signal of a phase detector if it is determined that the pulse signal is not within the normal locking range.

摘要翻译： 本发明涉及一种基于延迟锁定环的多相时钟发生器，其使用包括多个虚拟单元的压控延迟线从输入时钟信号产生多个多相时钟。 基于延迟锁定环的多相时钟发生器包括接收输入时钟和多个时钟的参考时钟的反谐波锁定电路，确定从输入时钟导出的脉冲信号是否在参考时钟的正常锁定范围内 并且如果确定脉冲信号不在正常锁定范围内，则输出强制控制信号来强制地控制相位检测器的输出信号。

公开(公告)号：US08817555B2

公开(公告)日：2014-08-26

申请号：US13478727

申请日：2012-05-23

申请人： Sung-Hwa Ok

发明人： Sung-Hwa Ok

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/229

摘要： A semiconductor memory device includes an internal signal generation unit configured to output a column select signal and a write enable signal in response to an external address, a write circuit unit configured to output internal data corresponding to external data in response to the write enable signal, a core unit configured to store the internal data in response to the column select signal, and an output timing control unit configured to control output timings of the internal signal generation unit and the write circuit unit in response to an external command, an internal synchronization signal, and preamble related information.

摘要翻译： 半导体存储器件包括：内部信号生成单元，被配置为响应于外部地址输出列选择信号和写使能信号;写电路单元，被配置为响应于写使能信号输出与外部数据对应的内部数据， 核心单元，被配置为响应于列选择信号来存储内部数据;以及输出定时控制单元，被配置为响应于外部命令来控制内部信号生成单元和写入电路单元的输出定时，内部同步信号 和前导码相关信息。

公开(公告)号：US20120137084A1

公开(公告)日：2012-05-31

申请号：US12965092

申请日：2010-12-10

申请人： Sung-Hwa OK

发明人： Sung-Hwa OK

IPC分类号： G11C7/22 ,  G06F12/00 ,  G11C7/10

CPC分类号： G11C7/1093 ,  G11C7/1066 ,  G11C7/222

摘要： A semiconductor memory device includes: an internal clock signal generation unit configured to generate an internal clock signal in response to an external clock signal; an internal data strobe signal generation unit configured to generate an internal data strobe signal in response to an external data strobe signal; a phase comparison unit configured to compare phases of the internal clock signal and the internal data strobe signal that are used in an enabled write path in response to an internal dummy write command with each other; and an output unit configured to output an output signal of the phase comparison unit.

摘要翻译： 半导体存储器件包括：内部时钟信号生成单元，被配置为响应于外部时钟信号产生内部时钟信号; 内部数据选通信号生成单元，被配置为响应于外部数据选通信号而生成内部数据选通信号; 相位比较单元，被配置为响应于内部虚拟写入命令来比较在使能写入路径中使用的内部时钟信号和内部数据选通信号的相位; 以及输出单元，被配置为输出所述相位比较单元的输出信号。

公开(公告)号：US20130155791A1

公开(公告)日：2013-06-20

申请号：US13478727

申请日：2012-05-23

申请人： Sung-Hwa OK

发明人： Sung-Hwa OK

IPC分类号： G11C7/22

CPC分类号： G11C7/22 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/229

摘要： A semiconductor memory device includes an internal signal generation unit configured to output a column select signal and a write enable signal in response to an external address, a write circuit unit configured to output internal data corresponding to external data in response to the write enable signal, a core unit configured to store the internal data in response to the column select signal, and an output timing control unit configured to control output timings of the internal signal generation unit and the write circuit unit in response to an external command, an internal synchronization signal, and preamble related information.

摘要翻译： 半导体存储器件包括：内部信号生成单元，被配置为响应于外部地址输出列选择信号和写使能信号;写电路单元，被配置为响应于写使能信号输出与外部数据对应的内部数据， 核心单元，被配置为响应于列选择信号来存储内部数据;以及输出定时控制单元，被配置为响应于外部命令来控制内部信号生成单元和写入电路单元的输出定时，内部同步信号 和前导码相关信息。

公开(公告)号：US20110291719A1

公开(公告)日：2011-12-01

申请号：US12970913

申请日：2010-12-16

申请人： Sung Hwa OK

发明人： Sung Hwa OK

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0805

摘要： Various exemplary embodiments of a phase correction circuit are disclosed. In one exemplary embodiment, the phase correction circuit may include a delay unit configured to delay a clock signal by a predetermined delay time and generate a delay clock signal, a delay line configured to delay a data strobe signal by a variable delay time in response to a delay control signal and generate a corrected data strobe signal, a phase detector configured to detect a phase difference between the delay clock signal and the corrected data strobe signal and generate a phase detection signal, and a shift register configured to generate the delay control signal in response to the phase detection signal.

摘要翻译： 公开了相位校正电路的各种示例性实施例。 在一个示例性实施例中，相位校正电路可以包括延迟单元，其被配置为将时钟信号延迟预定延迟时间并产生延迟时钟信号，延迟线被配置为响应于可变延迟时间延迟数据选通信号 延迟控制信号并产生校正数据选通信号;相位检测器，被配置为检测延迟时钟信号和校正数据选通信号之间的相位差，并产生相位检测信号;以及移位寄存器，被配置为产生延迟控制信号 响应于相位检测信号。

公开(公告)号：US08775761B2

公开(公告)日：2014-07-08

申请号：US12965092

申请日：2010-12-10

申请人： Sung-Hwa Ok

发明人： Sung-Hwa Ok

IPC分类号： G06F12/00

CPC分类号： G11C7/1093 ,  G11C7/1066 ,  G11C7/222

摘要： A semiconductor memory device includes: an internal clock signal generation unit configured to generate an internal clock signal in response to an external clock signal; an internal data strobe signal generation unit configured to generate an internal data strobe signal in response to an external data strobe signal; a phase comparison unit configured to compare phases of the internal clock signal and the internal data strobe signal that are used in an enabled write path in response to an internal dummy write command with each other; and an output unit configured to output an output signal of the phase comparison unit.

摘要翻译： 半导体存储器件包括：内部时钟信号生成单元，被配置为响应于外部时钟信号产生内部时钟信号; 内部数据选通信号生成单元，被配置为响应于外部数据选通信号而生成内部数据选通信号; 相位比较单元，被配置为响应于内部虚拟写入命令来比较在使能写入路径中使用的内部时钟信号和内部数据选通信号的相位; 以及输出单元，被配置为输出所述相位比较单元的输出信号。