Various exemplary embodiments of a phase correction circuit are disclosed. In one exemplary embodiment, the phase correction circuit may include a delay unit configured to delay a clock signal by a predetermined delay time and generate a delay clock signal, a delay line configured to delay a data strobe signal by a variable delay time in response to a delay control signal and generate a corrected data strobe signal, a phase detector configured to detect a phase difference between the delay clock signal and the corrected data strobe signal and generate a phase detection signal, and a shift register configured to generate the delay control signal in response to the phase detection signal.