公开(公告)号：US20080074141A1

公开(公告)日：2008-03-27

申请号：US11525275

申请日：2006-09-21

Applicant: Ket-Chong Yap ,  Senani Gunaratna ,  Wilma Waiman Shiao

Inventor： Ket-Chong Yap ,  Senani Gunaratna ,  Wilma Waiman Shiao

IPC: H03K19/177

CPC classification number: H03K19/17744 ,  H03K19/17732 ,  H03K19/17796

Abstract: An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.

Abstract translation: 集成电路包括可编程逻辑器件，专用器件和两者之间的接口电路。 可以容易地修改接口电路以适应可嵌入到集成电路中的各种专用设备的不同接口I / O需求。 在一个实施例中，接口电路可以使用多个掩码可编程单向接口缓冲电路来实现。 可以通过在集成电路的单个金属层中的接口缓冲电路中重新布线导体，基于期望的专用器件的需要来反转任何所需数量的接口缓冲电路的方向。 在另一个实施例中，接口电路可以使用硬件可配置的双向接口缓冲电路来实现。

公开(公告)号：US07184510B2

公开(公告)日：2007-02-27

申请号：US10672798

申请日：2003-09-26

Applicant: Soon-Gil Jung

Inventor： Soon-Gil Jung

IPC: H03D3/24 ,  H03L7/08

CPC classification number: H02M3/07 ,  H03L7/0896

Abstract: A differential charge pump includes a transient reducing circuit that provides multiple switching current paths to reduce transients caused by the charge transfer as the charge pump is switched. The differential charge pump includes separate current sources in the transient reducing circuit that are switchably coupled to the non-active current source in the charge pump. In one embodiment, each current sources include a static current source and a variable current source that is controlled by a common mode feedback circuit. The variable current source may produce a current with less magnitude than the current produced by the static current source.

Abstract translation: 差分电荷泵包括瞬态降低电路，其提供多个开关电流路径以减少当电荷泵切换时由电荷转移引起的瞬变。 差分电荷泵在瞬态降低电路中包括单独的电流源，其可切换地耦合到电荷泵中的非有功电流源。 在一个实施例中，每个电流源包括静态电流源和由共模反馈电路控制的可变电流源。 可变电流源可以产生比由静态电流源产生的电流更小的电流。

公开(公告)号：US6157207A

公开(公告)日：2000-12-05

申请号：US76367

申请日：1998-05-11

Applicant: David D. Eaton ,  Sudarshan Varshney ,  Paige A. Kolze

Inventor： David D. Eaton ,  Sudarshan Varshney ,  Paige A. Kolze

IPC: H01L21/8234 ,  H01L27/118 ,  G06F7/38 ,  H03K19/177

CPC classification number: H01L27/11807 ,  H01L21/823462

Abstract: To protect logic module output devices from high voltages, logic modules are not powered during antifuse programming. In some embodiments, two separate power input terminals VCC1 and VCC2 are provided: power input terminal VCC1 being coupled to power the logic modules, and power input terminal VCC2 being coupled to power the programming control circuitry. Power terminal VCC1 is left floating or is grounded during antifuse programming such that the logic modules are not powered but such that the programming circuitry is powered during antifuse programming via the second power terminal VCC2. Logic module output protection transistors are not required nor is the associated charge pump. Because the logic module input devices are not powered, a current surge through the input devices on power up does not occur and an internal disable signal and associated circuitry is not required. In one embodiment, the field programmable gate array is made smaller because it has no internal disable signal and associated circuitry, no logic module output protection transistors, and no charge pump that operates during normal circuit operation. In embodiments, power input terminal VCC2 is a high voltage compatible power input terminal.

Abstract translation: 为了保护逻辑模块输出设备免受高电压的影响，逻辑模块在反熔丝编程期间未通电。 在一些实施例中，提供两个单独的电源输入端子VCC1和VCC2：电源输入端子VCC1被耦合以对逻辑模块供电，并且电源输入端子VCC2被耦合以对编程控制电路供电。 电源端子VCC1在反熔丝编程期间处于悬空状态或接地状态，使得逻辑模块未通电，而使编程电路在反熔丝编程期间通过第二电源端子VCC2供电。 不需要逻辑模块输出保护晶体管，也不需要相关的电荷泵。 由于逻辑模块输入设备未通电，所以不会在上电时通过输入设备产生电流浪涌，并且不需要内部禁用信号和相关电路。 在一个实施例中，由于现场可编程门阵列没有内部禁用信号和相关联的电路，没有逻辑模块输出保护晶体管，并且没有在正常电路操作期间操作的电荷泵，所以现场可编程门阵列被制造得更 在实施例中，电源输入端子VCC2是高电压兼容电力输入端子。

公开(公告)号：US6148390A

公开(公告)日：2000-11-14

申请号：US662054

申请日：1996-06-12

Applicant: James MacArthur ,  Timothy M. Lacey

Inventor： James MacArthur ,  Timothy M. Lacey

IPC: G06F11/20 ,  G06F1/26

CPC classification number: H03K19/17764 ,  H03K19/17728 ,  H03K19/17736

Abstract: A programmable logic device having redundant sets of logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of sets of logic blocks, a plurality of routing resources and a programming circuit. Good logic blocks are enabled and fully operational when programmed. Nonfunctional logic blocks are disabled, powered off and invisible to the programming software. Each set of logic blocks has a corresponding routing resource. The routing resource corresponding to an enabled set of logic blocks is capable of being configured to provide input and output data paths for the enabled set of logic blocks. The routing resource corresponding to a disabled set of logic blocks is capable of being configured to bypass the disabled set of the logic blocks. The programming circuit stores the configuration data for the routing resources and is capable of providing the configuration data to a routing resource that corresponds to an enabled set of logic blocks.

公开(公告)号：US06107165A

公开(公告)日：2000-08-22

申请号：US133998

申请日：1998-08-13

Applicant: Rajiv Jain ,  Andre Stolmeijer ,  Mehul D. Shroff

Inventor： Rajiv Jain ,  Andre Stolmeijer ,  Mehul D. Shroff

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: A metal-to-metal conductive plug-type antifuise has a conductive plug disposed in an opening in an insulating layer. A programmable material feature (for example, amorphous silicon) overlies the conductive plug. A conductor involving a metal (for example, aluminum or copper) that migrates in the programmable material overlies the programmable material. To prevent migration of metal from the conductor into the programmable material when the antifuse is not programmed, the conductor has a layer of barrier metal between the metal that migrates and the programmable material. In some embodiments, there are two layers of barrier metal. An airbreak after formation of the first barrier metal layer improves the ability of the barrier metal to prevent diffusion between the programmable material and the overlying conductor. The airbreak may stuff grain boundaries in the upper surface of the first barrier metal and/or may cause the first barrier metal layer to have different grains and/or a different grain orientation than the overlaying second barrier metal layer. In some embodiments, a capping layer over the top surface of the programmable material protects the underlying programmable material during an ashing step when a mask used to etch the programmable material is removed. The capping layer and the programmable material form a capping layer/programmable material layer stack within the antifuse underneath the two barrier metal layers. The capping layer may also be made of a barrier metal and constitute an additional barrier.

Abstract translation: 金属对金属导电插塞型防腐剂具有设置在绝缘层的开口中的导电插塞。 可编程材料特征（例如，非晶硅）覆盖在导电插塞上。 涉及在可编程材料中迁移的金属（例如铝或铜）的导体覆盖在可编程材料上。 为了防止当反熔丝未编程时金属从导体迁移到可编程材料中，导体在迁移的金属和可编程材料之间具有一层阻挡金属。 在一些实施例中，存在两层屏障金属。 在形成第一阻挡金属层之后的空气破裂提高了阻挡金属防止可编程材料与上覆导体之间的扩散的能力。 所述防风剂可以在第一阻挡金属的上表面填充晶界，和/或可使第一阻挡金属层与覆盖的第二阻挡金属层具有不同的晶粒和/或不同的晶粒取向。 在一些实施例中，当可去除用于蚀刻可编程材料的掩模时，可编程材料顶表面上的覆盖层在灰化步骤期间保护底层可编程材料。 封盖层和可编程材料在两个阻挡金属层下面的反熔丝内形成覆盖层/可编程材料层堆叠。 封盖层也可以由阻挡金属制成并构成另外的屏障。

公开(公告)号：US6011408A

公开(公告)日：2000-01-04

申请号：US931870

申请日：1997-09-17

Applicant: Paige A. Kolze

Inventor： Paige A. Kolze

IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: A programmable integrated circuit (see FIG. 10) includes a routing conductor, i.e., "express wire," that extends substantially across the array of the integrated circuit. Because of the metal resistance through the long express wire, the express wire is simultaneously supplied with programming current from two different programming voltage terminals. Thus, programming current may be supplied to an electrode of an antifuse being programmed using programming current flowing through two separate programming voltage terminals. One programming voltage terminal supplies programming current via a first programming transistor and a first programming conductor to the express wire near one end of the programming conductor whereas another programming voltage terminal supplies programming current via a second programming transistor and a second programming conductor to the express wire near an opposite end of the express wire. The programming drivers that drive the first and second programming conductors are disposed adjacent opposite sides of the integrated circuit.

Abstract translation: 可编程集成电路（参见图10）包括基本上横跨集成电路的阵列延伸的布线导体，即“快速导线”。 由于通过长快速电线的金属电阻，快速电线同时由两个编程电压端子提供编程电流。 因此，可以使用流过两个单独的编程电压端子的编程电流将编程电流提供给正被编程的反熔丝的电极。 一个编程电压端子通过第一编程晶体管和第一编程导体向编程导体的一端附近的快速导线提供编程电流，而另一编程电压端通过第二编程晶体管和第二编程导体将编程电流提供给快速线 靠近快线的另一端。 驱动第一和第二编程导体的编程驱动器设置在集成电路的相对侧。

公开(公告)号：US5966028A

公开(公告)日：1999-10-12

申请号：US929654

申请日：1997-09-17

Applicant: James M. Apland

Inventor： James M. Apland

IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: A programmable integrated circuit (see FIG. 5) has a plurality of linearly extending wire segments with antifuses disposed between each wire segment and a plurality of linearly extending programming conductors that are perpendicular to the wire segments. A plurality of programming transistors are disposed between a corresponding respective one of the wire segments and a corresponding respective one of the programming conductors. A programming control conductor extending from a programming control driver is coupled to the gate electrode of each of the programming transistors as well as the gate electrode of a test transistor. A test antifuse is coupled in series with the test transistor. When the programming control conductor can drive the test transistor with an adequately high voltage to program the test antifuse, it is assumed that the programming control conductor can drive the programming transistor with an adequately high voltage to program the antifuses. The test transistor may be disposed on the programming control conductor at the opposite end from the programming control driver.

Abstract translation: 可编程集成电路（参见图5）具有多个线性延伸的线段，其中反熔丝设置在每个线段和垂直于线段的多个线性延伸的编程导体之间。 多个编程晶体管被布置在相应的一个线段和对应的相应的一个编程导体之间。 从编程控制驱动器延伸的编程控制导体耦合到每个编程晶体管的栅电极以及测试晶体管的栅电极。 测试反熔丝与测试晶体管串联耦合。 当编程控制导体可以用足够高的电压驱动测试晶体管来对测试反熔丝进行编程时，假设编程控制导体可以用足够高的电压来驱动编程晶体管来编程反熔丝。 测试晶体管可以设置在与编程控制驱动器相对的编程控制导体上。

公开(公告)号：US5898776A

公开(公告)日：1999-04-27

申请号：US754461

申请日：1996-11-21

Applicant: James M. Apland ,  David D. Eaton ,  Andrew K. Chan

Inventor： James M. Apland ,  David D. Eaton ,  Andrew K. Chan

IPC: G01R31/317 ,  G01R31/3185 ,  H04L9/00

CPC classification number: G01R31/318519 ,  G01R31/31719 ,  G01R31/318555 ,  G01R31/31702 ,  G01R31/318558

Abstract: A field programmable gate array has a security antifuse which when programmed prevents readout of data indicative of how the interconnect structure is programmed but which does not prevent readout of data indicative of which other antifuses are programmed. In some embodiments, the programming control shift registers adjacent the left and right sides are the field programmable gate array are disabled when the security antifuse is programmed but the programming control shift registers adjacent the top and bottom sides of the field programmable gate array are not disabled. A second security antifuse is also provided which when programmed disables a JTAG boundary scan register but does not disable a JTAG bypass register. Information can therefore be shifted through the JTAG test circuitry without allowing the JTAG circuitry to be used to extract information indicative of how the interconnect structure is programmed. Logic module and interface cell scan paths are provided and special test instructions are supported which allow test vectors to be loaded into the logic module and interface cell scan paths.

Abstract translation: 现场可编程门阵列具有安全反熔丝，其在编程时防止读出指示互连结构如何编程的数据，但是不防止读出指示哪个其它反熔丝被编程的数据。 在一些实施例中，当安全反熔丝被编程但是与现场可编程门阵列的顶侧和底侧相邻的编程控制移位寄存器未被禁用时，与左侧和右侧相邻的编程控制移位寄存器被禁用， 。 还提供了第二个安全反熔丝，当编程时禁用JTAG边界扫描寄存器，但不禁用JTAG旁路寄存器。 因此，信息可以通过JTAG测试电路转移，而不允许JTAG电路提取指示互连结构如何编程的信息。 提供逻辑模块和接口单元扫描路径，并支持特殊测试指令，允许将测试向量加载到逻辑模块和接口单元扫描路径中。

公开(公告)号：US5892370A

公开(公告)日：1999-04-06

申请号：US781985

申请日：1997-01-03

Applicant: David D. Eaton ,  Mukesh T. Lulla ,  Ker-Ching Liu

Inventor： David D. Eaton ,  Mukesh T. Lulla ,  Ker-Ching Liu

IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177 ,  H03K7/38 ,  H03K19/00

CPC classification number: H03K17/223 ,  H03K19/177

Abstract: A clock network of a field programmable gate array has a first clock bus extending across the chip in a first dimension. A clock pad can be coupled to the first clock bus if the clock network is to be driven from the clock pad. An output of a selected logic cell can be coupled to the first clock bus if the clock network is to be driven from a logic cell. To increase speed of the clock network, the first clock bus is segmented (in one embodiment, collinearly extending segments can be selectively coupled together via selectively programmable antifuses) so that only a short piece of the first clock bus is used to couple either the pad or the logic cell to the clock network in high speed applications.

Abstract translation: 现场可编程门阵列的时钟网络具有在第一维度上跨越芯片延伸的第一时钟总线。 如果时钟网络要从时钟焊盘驱动，则时钟焊盘可以耦合到第一个时钟总线。 如果要从逻辑单元驱动时钟网络，则所选逻辑单元的输出可以耦合到第一时钟总线。 为了增加时钟网络的速度，第一时钟总线被分段（在一个实施例中，共线延伸段可以通过有选择地可编程的反熔丝选择性地耦合在一起），使得仅使用第一时钟总线的短片来耦合焊盘 或逻辑单元到高速应用中的时钟网络。

公开(公告)号：US5729468A

公开(公告)日：1998-03-17

申请号：US520441

申请日：1995-08-29

Applicant: William D. Cox

Inventor： William D. Cox

IPC: G06F17/50 ,  H03K19/177 ,  G06F17/10

CPC classification number: G06F17/5054 ,  H03K19/17704

Abstract: Select sets of a logic function corresponding to an output of a first logic circuit are determined. These select sets are used to obtain a second logic circuit, the logic function corresponding to the output of which is the same as the logic function corresponding to the output of the first logic circuit. A propagation delay through the second logic circuit may be smaller than a corresponding delay through the first logic circuit. Sometimes, such a smaller propagation delay through the second logic circuit results in the second logic circuit having a smaller critical path delay. The second logic circuit may therefore have a greater maximum operating speed than the first logic circuit.

Abstract translation: 确定与第一逻辑电路的输出对应的逻辑功能的选择集。 这些选择组用于获得第二逻辑电路，对应于其输出的逻辑功能与对应于第一逻辑电路的输出的逻辑功能相同。 通过第二逻辑电路的传播延迟可以小于通过第一逻辑电路的对应延迟。 有时，通过第二逻辑电路的这种较小的传播延迟导致第二逻辑电路具有较小的关键路径延迟。 因此，第二逻辑电路可以具有比第一逻辑电路更大的最大工作速度。