Invention Grant
US5966028A Programming architecture for a programmable integrated circuit employing test antifuses and test transistors 失效
采用测试反熔丝和测试晶体管的可编程集成电路的编程架构

  • Patent Title: Programming architecture for a programmable integrated circuit employing test antifuses and test transistors
  • Patent Title (中): 采用测试反熔丝和测试晶体管的可编程集成电路的编程架构
  • Application No.: US929654
    Application Date: 1997-09-17
  • Publication No.: US5966028A
    Publication Date: 1999-10-12
  • Inventor: James M. Apland
  • Applicant: James M. Apland
  • Applicant Address: CA Sunnyvale
  • Assignee: QuickLogic Corporation
  • Current Assignee: QuickLogic Corporation
  • Current Assignee Address: CA Sunnyvale
  • Main IPC: H02H9/00
  • IPC: H02H9/00 H03K17/22 H03K19/177
Programming architecture for a programmable integrated circuit employing
test antifuses and test transistors
Abstract:
A programmable integrated circuit (see FIG. 5) has a plurality of linearly extending wire segments with antifuses disposed between each wire segment and a plurality of linearly extending programming conductors that are perpendicular to the wire segments. A plurality of programming transistors are disposed between a corresponding respective one of the wire segments and a corresponding respective one of the programming conductors. A programming control conductor extending from a programming control driver is coupled to the gate electrode of each of the programming transistors as well as the gate electrode of a test transistor. A test antifuse is coupled in series with the test transistor. When the programming control conductor can drive the test transistor with an adequately high voltage to program the test antifuse, it is assumed that the programming control conductor can drive the programming transistor with an adequately high voltage to program the antifuses. The test transistor may be disposed on the programming control conductor at the opposite end from the programming control driver.
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