公开(公告)号：US20150103451A1

公开(公告)日：2015-04-16

申请号：US14514066

申请日：2014-10-14

Applicant: Texas Instruments Incorporated

Inventor： Timothy Patrick Pauletti ,  Sameer Pendharkar ,  Wayne Tien-Feng Chen ,  Jonathan Brodsky ,  Robert Steinhoff

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L29/7436 ,  H01L29/749 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.

Abstract translation: 一种用于保护电路的输入/输出端子的静电放电（ESD）装置，该装置包括：第一晶体管，其具有耦合在电路的输入/输出（I / O）端子之间的集成硅控整流器（SCR） 节点和第二晶体管，其具有耦合在所述节点和电源电压的负端子之间的集成硅控整流器，其中所述第一晶体管的所述硅控整流器响应于ESD ESD电压而触发，并且所述可硅可控整流器 的第二晶体管响应于正的ESD电压而触发。

公开(公告)号：US11978814B2

公开(公告)日：2024-05-07

申请号：US17474492

申请日：2021-09-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： He Lin ,  Sameer Pendharkar

IPC: H01L31/0352 ,  H01L25/04 ,  H01L27/144 ,  H01L31/02 ,  H01L31/0216 ,  H01L31/0224 ,  H01L31/0304 ,  H01L31/103 ,  H01L31/18

CPC classification number: H01L31/035236 ,  H01L25/042 ,  H01L27/1443 ,  H01L27/1446 ,  H01L31/02005 ,  H01L31/02019 ,  H01L31/02164 ,  H01L31/022408 ,  H01L31/03048 ,  H01L31/1035 ,  H01L31/1848 ,  H01L31/1852

Abstract: A photo detector includes a superlattice with an undoped first semiconductor layer including undoped intrinsic semiconductor material, a doped second semiconductor layer having a first conductivity type on the first semiconductor layer, an undoped third semiconductor layer including undoped intrinsic semiconductor material on the second semiconductor layer, and a fourth semiconductor layer having a second opposite conductivity type on the third semiconductor layer, along with a first contact having the first conductivity type in the first, second, third, and fourth semiconductor layers, and a second contact having the second conductivity type and spaced apart from the first contact in the first, second, third, and fourth semiconductor layers. An optical shield on a second shielded portion of a top surface of the fourth semiconductor layer establishes electron and hole lakes. A packaging structure includes an opening that allows light to enter an exposed first portion of the top surface of the fourth semiconductor layer.

公开(公告)号：US11764208B2

公开(公告)日：2023-09-19

申请号：US17123413

申请日：2020-12-16

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  David LaFonteese ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/732 ,  H01L29/40

CPC classification number: H01L27/0259 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7818 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/732

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

公开(公告)号：US11721738B2

公开(公告)日：2023-08-08

申请号：US17197188

申请日：2021-03-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L23/528 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/4238 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/7835 ,  H01L23/528 ,  H01L29/1045 ,  H01L29/41758 ,  H01L29/42368

Abstract: An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

公开(公告)号：US20230132375A9

公开(公告)日：2023-04-27

申请号：US17123413

申请日：2020-12-16

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  David LaFonteese ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

公开(公告)号：US11355597B2

公开(公告)日：2022-06-07

申请号：US17153976

申请日：2021-01-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Tomomatsu ,  Sameer Pendharkar ,  Hiroshi Yamasaki

IPC: H01L23/48 ,  H01L29/40 ,  H01L29/778 ,  H01L29/423 ,  H01L23/482 ,  H01L29/20

Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

公开(公告)号：US11189721B2

公开(公告)日：2021-11-30

申请号：US16995133

申请日：2020-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Marie Denison ,  Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L29/51

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US11004971B2

公开(公告)日：2021-05-11

申请号：US16264848

申请日：2019-02-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer Pendharkar ,  Ming-yeh Chuang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: A power transistor is provided with at least one transistor finger that lies within a semiconductor material. The gate oxide is segmented into a set of segments with thick field oxide between each segment in order to reduce gate capacitance and thereby improve a resistance times gate charge figure of merit.

公开(公告)号：US10957774B2

公开(公告)日：2021-03-23

申请号：US16127281

申请日：2018-09-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L23/528 ,  H01L29/417 ,  H01L29/10

Abstract: An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

公开(公告)号：US10861943B2

公开(公告)日：2020-12-08

申请号：US16216874

申请日：2018-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/66

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a first GaN-based alloy layer having a top side and disposed on the GaN layer; a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer.