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公开(公告)号：US09483869B2
公开(公告)日：2016-11-01
申请号：US14274958
申请日：2014-05-12
Applicant: Intel Corporation
Inventor： Carl J. Munkberg , Karthik Vaidyanathan , Jon N. Hasselgren , Franz P. Clarberg , Tomas G. Akenine-Moller , Marco Salvi
CPC classification number: G06T15/503 , G06T5/50 , G06T15/06 , G06T15/50 , G06T15/506 , G06T2200/21 , G06T2207/10052 , H04N5/23229
Abstract: Real-time light field reconstruction for defocus blur may be used to handle the case of simultaneous defocus and motion blur. By carefully introducing a few approximations, a very efficient sheared reconstruction filter is derived, which produces high quality images even for a very low number of input samples in some embodiments. The algorithm may be temporally robust, and is about two orders of magnitude faster than previous work, making it suitable for both real-time rendering and as a post-processing pass for high quality rendering in some embodiments.
Abstract translation: 用于散焦模糊的实时光场重建可用于处理同时散焦和运动模糊的情况。 通过仔细地引入几个近似值，导出非常有效的剪切重建滤波器，即使在一些实施例中对于非常低数量的输入样本也可产生高质量图像。 该算法可以在时间上是稳健的，并且比以前的工作快两个数量级，使得它在一些实施例中适合于实时渲染和用于高质量渲染的后处理通行。
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公开(公告)号：US12236519B2
公开(公告)日：2025-02-25
申请号：US18090810
申请日：2022-12-29
Applicant: INTEL CORPORATION
Inventor： Karthik Vaidyanathan , Michael Apodaca , Thomas Raoux , Carsten Benthin , Kai Xiao , Carson Brownlee , Joshua Barczak
Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.
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公开(公告)号：US12223585B2
公开(公告)日：2025-02-11
申请号：US18376098
申请日：2023-10-03
Applicant: INTEL CORPORATION
Inventor： Karol Szerszen , Prasoonkumar Surti , Gabor Liktor , Karthik Vaidyanathan , Sven Woop
Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.
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94.发明授权公开(公告)号：US12125133B2
公开(公告)日：2024-10-22
申请号：US18371614
申请日：2023-09-22
Applicant: Intel Corporation
Inventor： Gabor Liktor , Karthik Vaidyanathan , Jefferson Amstutz , Atsuo Kuwahara , Michael Doyle , Travis Schluessler
CPC classification number: G06T15/005 , G06T1/60 , G06T15/06 , G06T2210/21
Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.
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公开(公告)号：US12045658B2
公开(公告)日：2024-07-23
申请号：US17589689
申请日：2022-01-31
Applicant: Intel Corporation
Inventor： Pawel Majewski , Prasoonkumar Surti , Karthik Vaidyanathan , Joshua Barczak , Vasanth Ranganathan , Vikranth Vemulapalli
CPC classification number: G06F9/5027 , G06F9/4881 , G06F9/54
Abstract: Apparatus and method for stack access throttling for synchronous ray tracing. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations to ensure that a size of the active ray tracing stack allocations remains within a threshold; and an execution unit to execute a thread to explicitly request a new ray tracing stack allocation from the ray tracing acceleration hardware, the ray tracing acceleration hardware to permit the new ray tracing stack allocation if the size of the active ray tracing stack allocations will remain within the threshold after permitting the new ray tracing stack allocation.
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Patent Agency Ranking
公开(公告)号：US11880928B2
公开(公告)日：2024-01-23
申请号：US17723772
申请日：2022-04-19
Applicant: INTEL CORPORATION
Inventor： Scott Janus , Prasoonkumar Surti , Karthik Vaidyanathan , Alexey Supikov , Gabor Liktor , Carsten Benthin , Philip Laws , Michael Doyle
CPC classification number: G06T15/06 , G06T1/60 , G06T15/005 , G06T17/005 , G06T2210/21
Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
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公开(公告)号：US11875453B2
公开(公告)日：2024-01-16
申请号：US17222347
申请日：2021-04-05
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Marco Salvi , Robert M. Toth
CPC classification number: G06T15/503 , G06T1/20 , G06T2200/12
Abstract: In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. Examples where the shading rate may be reduced include areas where there is motion and camera defocus, areas of peripheral blur, and in general, any case where the visibility is reduced anyway. The shading rate may be changed in a region, such as a shading quad, by changing the size of the region.
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公开(公告)号：US11783530B2
公开(公告)日：2023-10-10
申请号：US17677109
申请日：2022-02-22
Applicant: INTEL CORPORATION
Inventor： Karol Szerszen , Prasoonkumar Surti , Gabor Liktor , Karthik Vaidyanathan , Sven Woop
CPC classification number: G06T15/06 , G06T1/20 , G06T15/005 , G06T15/08 , G06T17/10
Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.
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公开(公告)号：US11776195B2
公开(公告)日：2023-10-03
申请号：US17463320
申请日：2021-08-31
Applicant: Intel Corporation
Inventor： John G. Gierach , Karthik Vaidyanathan , Thomas F. Raoux
CPC classification number: G06T15/005 , G06F9/4887
Abstract: Examples are described here that can be used to enable a main routine to request subroutines or other related code to be executed with other instantiations of the same subroutine or other related code for parallel execution. A sorting unit can be used to accumulate requests to execute instantiations of the subroutine. The sorting unit can request execution of a number of multiple instantiations of the subroutine corresponding to a number of lanes in a SIMD unit. A call stack can be used to share information to be accessed by a main routine after execution of the subroutine completes.
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公开(公告)号：US11688122B2
公开(公告)日：2023-06-27
申请号：US17591166
申请日：2022-02-02
Applicant: Intel Corporation
Inventor： Devan Burke , Adam T. Lake , Jeffery S. Boles , John H. Feit , Karthik Vaidyanathan , Abhishek R. Appu , Joydeep Ray , Subramaniam Maiyuran , Altug Koker , Balaji Vembu , Murali Ramadoss , Prasoonkumar Surti , Eric J. Hoekstra , Gabor Liktor , Jonathan Kennedy , Slawomir Grajewski , Elmoustapha Ould-Ahmed-Vall
CPC classification number: G06T15/005 , G06F9/4881 , G06T15/04 , G06T15/80 , G06T17/10 , G06T17/20
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.
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