公开(公告)号：US10957095B2

公开(公告)日：2021-03-23

申请号：US16056222

申请日：2018-08-06

申请人： Intel Corporation

发明人： Karthik Vaidyanathan ,  Won-Jong Lee ,  Gabor Liktor ,  John G. Gierach ,  Pawel Majewski ,  Prasoonkumar Surti ,  Carsten Benthin ,  Sven Woop ,  Thomas Raoux

IPC分类号： G06T15/00 ,  G06T15/06 ,  G06T15/80 ,  G06T1/60 ,  G09G5/36

摘要： Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.

公开(公告)号：US12045658B2

公开(公告)日：2024-07-23

申请号：US17589689

申请日：2022-01-31

申请人： Intel Corporation

发明人： Pawel Majewski ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Joshua Barczak ,  Vasanth Ranganathan ,  Vikranth Vemulapalli

IPC分类号： G06F9/50 ,  G06F9/48 ,  G06F9/54

CPC分类号： G06F9/5027 ,  G06F9/4881 ,  G06F9/54

摘要： Apparatus and method for stack access throttling for synchronous ray tracing. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations to ensure that a size of the active ray tracing stack allocations remains within a threshold; and an execution unit to execute a thread to explicitly request a new ray tracing stack allocation from the ray tracing acceleration hardware, the ray tracing acceleration hardware to permit the new ray tracing stack allocation if the size of the active ray tracing stack allocations will remain within the threshold after permitting the new ray tracing stack allocation.

公开(公告)号：US20230298127A1

公开(公告)日：2023-09-21

申请号：US17699066

申请日：2022-03-18

申请人： Intel Corporation

发明人： Joshua Barczak ,  Sven WOOP ,  Pawel Majewski ,  Radoslaw DRABINSKI

IPC分类号： G06T1/60 ,  G06T15/06 ,  G06T15/10 ,  G06V10/44 ,  G06V10/74

CPC分类号： G06T1/60 ,  G06T15/06 ,  G06T15/10 ,  G06V10/44 ,  G06V10/761 ,  G06T2210/12 ,  G06T2210/21

摘要： Apparatus and method for a biased BVH traversal path. For example, one embodiment of an apparatus comprises: ray tracing traversal hardware logic to traverse a ray through nodes of a bounding volume hierarchy (BVH); and stack management hardware logic to push and pop entries on a traversal stack, each entry corresponding to a node of the BVH, wherein the ray tracing traversal hardware logic is to determine an order in which to push entries to the traversal stack based on both a first intersection value corresponding to a closest intersection point between the ray and a BVH node and a farthest intersection value between the ray and the BVH node. In addition, the ray traversal hardware logic may determine the order in which to push the entries to the traversal stack further based on a probability density value corresponding to a probability of a ray hitting geometry inside of the BVH.

公开(公告)号：US20230298126A1

公开(公告)日：2023-09-21

申请号：US17699059

申请日：2022-03-18

申请人： INTEL CORPORATION

发明人： Sven Woop ,  Carsten Benthin ,  Prasoonkumar Surti ,  Joshua Barczak ,  Abhishek R. Appu ,  Pawel Majewski

IPC分类号： G06T1/60 ,  G06T1/20 ,  G06T15/10 ,  G06T15/06 ,  G06F12/0862 ,  G06F12/0811

CPC分类号： G06T1/60 ,  G06T1/20 ,  G06T15/10 ,  G06T15/06 ,  G06F12/0862 ,  G06F12/0811

摘要： Apparatus and method for prefetching node data. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations within a traversal stack; and stack management hardware logic to issue a prefetch operation comprising an indication of bounding volume hierarchy (BVH) node data to be prefetched and an indication of a cache level, wherein responsive to performing the prefetch operation, the BVH node data is to be prefetched to the indicated cache level.