公开(公告)号：US09502577B2

公开(公告)日：2016-11-22

申请号：US14416227

申请日：2014-04-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ke Wang ,  Seongyeol Yoo ,  Ce Ning ,  Wei Yang

IPC: H01L29/786 ,  H01L21/4763 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L21/47635 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78606

Abstract: Provided are oxide thin-film transistor and display device employing the same, and method for manufacturing an oxide thin-film transistor array substrate. A source electrode and a drain electrode are located below an oxide active layer pattern, and a gate electrode is located below the source electrode and the drain electrode, and the gate insulating layer is located between the gate electrode and the source electrode/the drain electrode.

Abstract translation: 提供了氧化物薄膜晶体管和采用该氧化物薄膜晶体管的显示装置，以及制造氧化物薄膜晶体管阵列基板的方法。 源电极和漏极位于氧化物有源层图案的下方，栅电极位于源极和漏电极的下方，栅极绝缘层位于栅电极和源电极/漏电极之间 。

公开(公告)号：US09502436B2

公开(公告)日：2016-11-22

申请号：US14408049

申请日：2014-04-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ce Ning

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/49 ,  H01L29/786 ,  H01L29/45 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: H01L27/1225 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/7869

Abstract: A thin film transistor, an array substrate and a method for fabricating the array substrate, and a display device are disclosed. The thin film transistor comprises a gate electrode, a gate insulation layer, a semiconductor active layer, a source electrode, a drain electrode and a protection layer provided on a base substrate, and comprises: a first transparent electrode provided between the source electrode and the semiconductor active layer, corresponding to the source electrode and in direct contact with the source electrode; a second transparent electrode provided between the drain electrode and the semiconductor active layer, corresponding to the drain electrode and in direct contact with the drain electrode, the first transparent electrode is in contact with the semiconductor active layer through a first via provided in the protection layer, the second transparent electrode is in contact with the semiconductor active layer through a second via provided in the protection layer.

Abstract translation: 公开了薄膜晶体管，阵列基板和阵列基板的制造方法以及显示装置。 薄膜晶体管包括：设置在基极基板上的栅电极，栅极绝缘层，半导体有源层，源电极，漏电极和保护层，并且包括：第一透明电极，设置在源极和 半导体有源层，对应于源电极并与源电极直接接触; 第二透明电极，设置在漏电极和半导体有源层之间，对应于漏极并与漏电极直接接触，第一透明电极通过设置在保护层中的第一通孔与半导体有源层接触 第二透明电极通过设置在保护层中的第二通孔与半导体有源层接触。

公开(公告)号：US09178046B2

公开(公告)日：2015-11-03

申请号：US13703112

申请日：2012-09-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ce Ning

IPC: H01L21/00 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L27/1288 ,  H01L29/66765 ,  H01L29/7869

Abstract: Embodiment of the present invention disclose an array substrate and a manufacturing method thereof, and the manufacturing method of an array substrate comprises the following steps: Step S1: a gate electrode metal layer, an insulating layer and an active layer are deposited successively on a substrate, and gate electrodes, gate lines and an active layer pattern are formed through a first mask process; Step S2: a protective layer is deposited on the substrate after completion of the step S1, and via-holes are formed in the protective layer through a second mask process; and Step S3: a pixel electrode layer and a source/drain electrode metal layer are deposited sequentially on the substrate after completion of the step S2, and source/drain electrodes, pixel electrodes and data lines are formed through a third mask process.

Abstract translation: 本发明的实施例公开了一种阵列基板及其制造方法，其阵列基板的制造方法包括以下步骤：步骤S1：将栅电极金属层，绝缘层和有源层依次沉积在基板上 通过第一掩模工艺形成栅电极，栅极线和有源层图案; 步骤S2：在步骤S1完成之后，在基板上沉积保护层，并且通过第二掩模工艺在保护层中形成通孔; 步骤S3：在步骤S2完成之后，在基板上依次沉积像素电极层和源极/漏极电极金属层，并且通过第三掩模处理形成源极/漏极，像素电极和数据线。

公开(公告)号：US20150303222A1

公开(公告)日：2015-10-22

申请号：US14408049

申请日：2014-04-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ce Ning

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/49 ,  H01L29/786 ,  H01L29/45

CPC classification number: H01L27/1225 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/7869

Abstract: A thin film transistor, an array substrate and a method for fabricating the array substrate, and a display device are disclosed. The thin film transistor comprises a gate electrode, a gate insulation layer, a semiconductor active layer, a source electrode, a drain electrode and a protection layer provided on a base substrate, and comprises: a first transparent electrode provided between the source electrode and the semiconductor active layer, corresponding to the source electrode and in direct contact with the source electrode; a second transparent electrode provided between the drain electrode and the semiconductor active layer, corresponding to the drain electrode and in direct contact with the drain electrode, the first transparent electrode is in contact with the semiconductor active layer through a first via provided in the protection layer, the second transparent electrode is in contact with the semiconductor active layer through a second via provided in the protection layer.

Abstract translation: 公开了薄膜晶体管，阵列基板和阵列基板的制造方法以及显示装置。 薄膜晶体管包括：设置在基极基板上的栅电极，栅极绝缘层，半导体有源层，源电极，漏电极和保护层，并且包括：第一透明电极，设置在源极和 半导体有源层，对应于源电极并与源电极直接接触; 第二透明电极，设置在漏电极和半导体有源层之间，对应于漏极并与漏电极直接接触，第一透明电极通过设置在保护层中的第一通孔与半导体有源层接触 第二透明电极通过设置在保护层中的第二通孔与半导体有源层接触。

公开(公告)号：US08952387B2

公开(公告)日：2015-02-10

申请号：US13822920

申请日：2012-11-28

Applicant: BOE Technology Group Co., Ltd.

Inventor： Ce Ning ,  Xuehui Zhang ,  Jing Yang

IPC: H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H01L29/10 ,  H01L29/12 ,  H01L31/0376 ,  H01L31/20 ,  H01L31/062 ,  H01L31/113 ,  H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L21/3213 ,  G02F1/1362

CPC classification number: H01L27/1225 ,  G02F2001/136236 ,  G02F2001/13629 ,  H01L21/32139 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1288

Abstract: According to embodiments of the present invention, there are provided a TFT array substrate, a method for manufacturing the TFT array substrate and an electronic device. The method for manufacturing the TFT array substrate includes: a first patterning process, in which a pattern of a pixel electrode formed by a first transparent conductive layer and patterns of a drain electrode and a source electrode that are separated from each other and a data line, which are formed by a first metal layer, are formed on a transparent substrate; a second patterning process, in which a pattern of a gate insulating layer and a pattern of an active layer formed by a transparent oxide layer are formed on the transparent substrate subjected to the first patterning process; and a third patterning process, in which a pattern of a common electrode formed by a second transparent conductive layer and patterns of a gate electrode and a gate line which are formed by a second metal layer are formed on the transparent substrate subjected to the second patterning process.

Abstract translation: 根据本发明的实施例，提供了TFT阵列基板，TFT阵列基板的制造方法和电子设备。 制造TFT阵列基板的方法包括：第一图案形成工艺，其中由第一透明导电层形成的像素电极的图案和彼此分离的漏极和源电极的图案以及数据线 由第一金属层形成，形成在透明基板上; 第二图案化工艺，其中在经过第一图案化工艺的透明衬底上形成栅极绝缘层的图案和由透明氧化物层形成的有源层的图案; 以及第三图案化工艺，其中通过第二透明导电层形成的公共电极的图案和由第二金属层形成的栅电极和栅极线的图案形成在经过第二图案化的透明基板上 处理。

公开(公告)号：US20140183519A1

公开(公告)日：2014-07-03

申请号：US13822920

申请日：2012-11-28

Applicant: BOE TECHNOLOGY GROUP CO. LTD.

Inventor： Ce Ning ,  Xuehui Zhang ,  Jing Yang

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  G02F2001/136236 ,  G02F2001/13629 ,  H01L21/32139 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1288

Abstract: According to embodiments of the present invention, there are provided a TFT array substrate, a method for manufacturing the TFT array substrate and an electronic device. The method for manufacturing the TFT array substrate comprises: a first patterning process, in which a pattern of a pixel electrode formed by a first transparent conductive layer and patterns of a drain electrode and a source electrode that are separated from each other and a data line, which are formed by a first metal layer, are formed on a transparent substrate; a second patterning process, in which a pattern of a gate insulating layer and a pattern of an active layer formed by a transparent oxide layer are formed on the transparent substrate subjected to the first patterning process; and a third patterning process, in which a pattern of a common electrode formed by a second transparent conductive layer and patterns of a gate electrode and a gate line which are formed by a second metal layer are formed on the transparent substrate subjected to the second patterning process.

Abstract translation: 根据本发明的实施例，提供了TFT阵列基板，TFT阵列基板的制造方法和电子设备。 制造TFT阵列基板的方法包括：第一图案化工艺，其中由第一透明导电层形成的像素电极的图案以及彼此分离的漏电极和源电极的图案以及数据线 由第一金属层形成，形成在透明基板上; 第二图案化工艺，其中在经过第一图案化工艺的透明衬底上形成栅极绝缘层的图案和由透明氧化物层形成的有源层的图案; 以及第三图案化工艺，其中通过第二透明导电层形成的公共电极的图案和由第二金属层形成的栅电极和栅极线的图案形成在经过第二图案化的透明基板上 处理。

公开(公告)号：US20140091331A1

公开(公告)日：2014-04-03

申请号：US13703483

申请日：2012-09-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ce Ning ,  Xuehui Zhang ,  Jing Yang

IPC: H01L27/12

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/3248 ,  H01L27/326

Abstract: The embodiments of the invention provide a display device, a thin film transistor, an array substrate and a manufacturing method thereof. The manufacturing method comprises: step A, forming patterns of a source electrode, a drain electrode, a data line and a pixel electrode; step B, forming an active layer and agate insulating layer in order, and forming a via hole in the gate insulating layer for connecting the data line and an external circuit; and step C, forming patterns of a gate electrode, a gate line and a common electrode line, or forming a pattern of a gate electrode, a gate line and a common electrode.

Abstract translation: 本发明的实施例提供一种显示装置，薄膜​​晶体管，阵列基板及其制造方法。 制造方法包括：步骤A，形成源电极，漏电极，数据线和像素电极的图案; 步骤B，依次形成有源层和玛瑙绝缘层，并在用于连接数据线和外部电路的栅极绝缘层中形成通孔; 和步骤C，形成栅电极，栅极线和公共电极线的图案，或形成栅电极，栅极线和公共电极的图案。

公开(公告)号：US20140054580A1

公开(公告)日：2014-02-27

申请号：US13703112

申请日：2012-09-26

Applicant: BOE Technology Group Co., LTD.

Inventor： Ce Ning

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L27/1288 ,  H01L29/66765 ,  H01L29/7869

Abstract: Embodiment of the present invention disclose an array substrate and a manufacturing method thereof, and the manufacturing method of an array substrate comprises the following steps: Step S1: a gate electrode metal layer, an insulating layer and an active layer are deposited successively on a substrate, and gate electrodes, gate lines and an active layer pattern are formed through a first mask process; Step S2: a protective layer is deposited on the substrate after completion of the step S1, and via-holes are formed in the protective layer through a second mask process; and Step S3: a pixel electrode layer and a source/drain electrode metal layer are deposited sequentially on the substrate after completion of the step S2, and source/drain electrodes, pixel electrodes and data lines are formed through a third mask process.

Abstract translation: 本发明的实施例公开了一种阵列基板及其制造方法，其阵列基板的制造方法包括以下步骤：步骤S1：将栅电极金属层，绝缘层和有源层依次沉积在基板上 通过第一掩模工艺形成栅电极，栅极线和有源层图案; 步骤S2：在步骤S1完成之后，在基板上沉积保护层，并且通过第二掩模工艺在保护层中形成通孔; 步骤S3：在步骤S2完成之后，在基板上依次沉积像素电极层和源极/漏极电极金属层，并且通过第三掩模处理形成源极/漏极，像素电极和数据线。