公开(公告)号：US10719917B2

公开(公告)日：2020-07-21

申请号：US16243490

申请日：2019-01-09

申请人： Tomer Bar-On ,  Hugues Labbe ,  Adam T. Lake ,  Kai Xiao ,  Ankur N. Shah ,  Johannes Guenther ,  Abhishek R. Appu ,  Joydeep Ray ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall

发明人： Tomer Bar-On ,  Hugues Labbe ,  Adam T. Lake ,  Kai Xiao ,  Ankur N. Shah ,  Johannes Guenther ,  Abhishek R. Appu ,  Joydeep Ray ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall

IPC分类号： G06T5/00 ,  G06T1/20 ,  G06T15/00 ,  G06T15/50 ,  G06T9/00 ,  G06T11/40

摘要： Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.

公开(公告)号：US10564966B2

公开(公告)日：2020-02-18

申请号：US13977171

申请日：2011-12-22

申请人： Bret L. Toll ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Elmoustapha Ould-Ahmed Vall ,  Mark J. Charney

发明人： Bret L. Toll ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Elmoustapha Ould-Ahmed Vall ,  Mark J. Charney

IPC分类号： G06F9/30

摘要： A method of an aspect includes receiving a packed data operation mask shift instruction. The packed data operation mask shift instruction indicates a source having a packed data operation mask, indicates a shift count number of bits, and indicates a destination. The method further includes storing a result in the destination in response to the packed data operation mask shift instruction. The result includes a sequence of bits of the packed data operation mask that have been shifted by the shift count number of bits. Other methods, apparatus, systems, and instructions are disclosed.

公开(公告)号：US20190102176A1

公开(公告)日：2019-04-04

申请号：US15721261

申请日：2017-09-29

申请人： VENKATESWARA MADDURI ,  ELMOUSTAPHA OULD-AHMED-VALL ,  MARK CHARNEY ,  ROBERT VALENTINE ,  JESUS CORBAL ,  BINWEI YANG

发明人： VENKATESWARA MADDURI ,  ELMOUSTAPHA OULD-AHMED-VALL ,  MARK CHARNEY ,  ROBERT VALENTINE ,  JESUS CORBAL ,  BINWEI YANG

IPC分类号： G06F9/30

摘要： An apparatus and method for performing dual concurrent multiplications of packed data elements. For example one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed doubleword data elements; a second source register to store a second plurality of packed doubleword data elements; and execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to multiply a first doubleword data element from the first source register with a second doubleword data element from the second source register to generate a first quadword product and to concurrently multiply a third doubleword data element from the first source register with a fourth doubleword data element from the second source register to generate a second quadword product; and a destination register to store the first quadword product and the second quadword product as first and second packed quadword data elements.

公开(公告)号：US10120680B2

公开(公告)日：2018-11-06

申请号：US15396184

申请日：2016-12-30

申请人： Rama Kishan V. Malladi ,  Elmoustapha Ould-Ahmed-Vall

发明人： Rama Kishan V. Malladi ,  Elmoustapha Ould-Ahmed-Vall

IPC分类号： G06F9/30

摘要： Embodiments of systems, apparatuses, and methods for broadcast arithmetic in a processor are described. For example, execution circuitry executes a decoded instruction to broadcast a data value from a least significant packed data element position of a first packed data source operand to a plurality of arithmetic circuits and for each packed data element position of a second packed data source operand, other than a least significant packed data element position, perform the arithmetic operation defined by the instruction on a data value from that packed data element position of the second packed data source operand and all data values from packed data element positions of the second packed data source operand that are of lesser position significance to the broadcast data value from the least significant packed data element position of the first packed data source operand, and stores a result of each arithmetic operation into a packed data element position of the packed data destination operand that corresponds to a most significant packed data element position of the second packed data source operand.

公开(公告)号：US10083032B2

公开(公告)日：2018-09-25

申请号：US13993321

申请日：2011-12-14

申请人： Suleyman Sair ,  Elmoustapha Ould-Ahmed-Vall

发明人： Suleyman Sair ,  Elmoustapha Ould-Ahmed-Vall

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/345 ,  G06F9/32

CPC分类号： G06F9/30065 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/325 ,  G06F9/345 ,  G06F9/3824

摘要： A loop alignment instruction indicates a base address of an array as a first operand, an iteration limit of a loop as a second operand, and a destination. The loop contains iterations and each iteration includes a data element of the array. A processor receives the loop alignment instruction, decodes the instruction for execution, and stores a result of the execution in the destination. The result indicates the number of data elements at a beginning of the array that are to be handled separately from a remaining portion of the array, such that the base address of the remaining portion of the array aligns with an alignment width.

公开(公告)号：US20180189058A1

公开(公告)日：2018-07-05

申请号：US15396184

申请日：2016-12-30

申请人： Rama Kishan V. MALLADI ,  Elmoustapha OULD-AHMED-VALL

发明人： Rama Kishan V. MALLADI ,  Elmoustapha OULD-AHMED-VALL

IPC分类号： G06F9/30

CPC分类号： G06F9/3001 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/3017

摘要： Embodiments of systems, apparatuses, and methods for broadcast arithmetic in a processor are described. For example, execution circuitry executes a decoded instruction to broadcast a data value from a least significant packed data element position of a first packed data source operand to a plurality of arithmetic circuits and for each packed data element position of a second packed data source operand, other than a least significant packed data element position, perform the arithmetic operation defined by the instruction on a data value from that packed data element position of the second packed data source operand and all data values from packed data element positions of the second packed data source operand that are of lesser position significance to the broadcast data value from the least significant packed data element position of the first packed data source operand, and stores a result of each arithmetic operation into a packed data element position of the packed data destination operand that corresponds to a most significant packed data element position of the second packed data source operand.

公开(公告)号：US20170192780A1

公开(公告)日：2017-07-06

申请号：US14984078

申请日：2015-12-30

申请人： Robert Valentine ,  Elmoustapha Ould-Ahmed-Vall ,  Jason W. Brandt ,  Mark J. Charney ,  Ashish Jha ,  Milind B. Girkar ,  Bret L. Toll ,  Evgeny V. Stupachenko ,  Sergey Y. Ostanevich

发明人： Robert Valentine ,  Elmoustapha Ould-Ahmed-Vall ,  Jason W. Brandt ,  Mark J. Charney ,  Ashish Jha ,  Milind B. Girkar ,  Bret L. Toll ,  Evgeny V. Stupachenko ,  Sergey Y. Ostanevich

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30192

摘要： Embodiments of systems, apparatuses, and method for getting even or odd data elements are described. For example, in some embodiments, an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields for a first source operand, a second source operand, and a destination operand; and execution circuitry to execute the decoded instruction to extract data elements from even data element positions of the first and second source operands and store the extracted data elements into the destination operand.

公开(公告)号：US09619226B2

公开(公告)日：2017-04-11

申请号：US13992230

申请日：2011-12-23

申请人： Mostafa Hagog ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Amit Gradstein ,  Simon Rubanovich ,  Zeev Sperber

发明人： Mostafa Hagog ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Amit Gradstein ,  Simon Rubanovich ,  Zeev Sperber

IPC分类号： G06F9/302 ,  G06F9/305 ,  G06F15/76 ,  G06F9/30 ,  G06F15/80

CPC分类号： G06F9/30036 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30167 ,  G06F9/30185 ,  G06F15/8053 ,  G06F2207/5442

摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal add or subtract of packed data elements in response to a single vector packed horizontal add or subtract instruction that includes a destination vector register operand, a source vector register operand, and an opcode are describes.

公开(公告)号：US20160357556A1

公开(公告)日：2016-12-08

申请号：US14582820

申请日：2014-12-24

申请人： Elmoustapha OULD-AHMED-VALL ,  Christopher J. HUGHES ,  Robert VALENTINE ,  Milind B. GIRKAR

发明人： Elmoustapha OULD-AHMED-VALL ,  Christopher J. HUGHES ,  Robert VALENTINE ,  Milind B. GIRKAR

IPC分类号： G06F9/30 ,  G06F12/0875

CPC分类号： G06F9/3016 ,  G06F9/3013 ,  G06F9/3842 ,  G06F12/0875 ,  G06F2212/452

摘要： Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode, and execution hardware to execute the decoded instruction to continue a data speculative execution (DSX) and to determine that a DSX loop iteration is to be committed, commit speculative stores associated with the DSX loop iteration, and start a new DSX loop iteration.

摘要翻译： 描述用于数据推测执行（DSX）的系统，方法和装置。 在一些实施例中，用于执行DSX的硬件装置包括硬件解码器来解码指令，包括操作码的指令和执行硬件，以执行解码指令以继续数据推测执行（DSX）并确定DSX循环 迭代将被提交，提交与DSX循环迭代关联的推测存储，并启动新的DSX循环迭代。

公开(公告)号：US09513918B2

公开(公告)日：2016-12-06

申请号：US13995974

申请日：2011-12-22

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Mostafa Hagog ,  Jesus Corbal ,  Bret L Toll ,  Mark J Charney ,  Tal Uliel ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Mostafa Hagog ,  Jesus Corbal ,  Bret L Toll ,  Mark J Charney ,  Tal Uliel ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30196 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3867

摘要： An apparatus and method are described for permuting data elements with masking. For example, a method according to one embodiment includes the following operations: reading values from a mask data structure to determine whether masking is implemented for each data element of a destination operand; if masking not implemented for a particular data element, then selecting data elements from a first source operand and a second source operand based on index values stored in destination operand to be copied to data element positions within the destination operand, wherein any one of the data elements from either the first source operand and the second source operand may be copied to any one of the data element positions within the destination operand; and if masking is implemented for a particular data element of the destination operand, then performing a designated masking operation with respect to that particular data element.

摘要翻译： 描述了用掩模来置换数据元素的装置和方法。 例如，根据一个实施例的方法包括以下操作：从掩模数据结构读取值以确定是否对目的地操作数的每个数据元素实施掩蔽; 如果对于特定数据元素没有被实现掩蔽，则基于存储在目的地操作数中的索引值从第一源操作数和第二源操作数中选择数据元素以被复制到目的地操作数中的数据元素位置，其中数据中的任何一个 可以将来自第一源操作数和第二源操作数的元素复制到目的地操作数中的任何一个数据元素位置; 并且如果针对目的地操作数的特定数据元素实现掩蔽，则对该特定数据元素执行指定的掩蔽操作。