公开(公告)号：US08742490B2

公开(公告)日：2014-06-03

申请号：US13099252

申请日：2011-05-02

Applicant: Donald R. Disney

Inventor： Donald R. Disney

IPC: H01L29/772 ,  H01L21/60

CPC classification number: H01L23/49575 ,  H01L21/823487 ,  H01L23/3121 ,  H01L23/49562 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0688 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73257 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present technology is directed generally to a semiconductor device. In one embodiment, the semiconductor device includes a first vertical transistor and a second vertical transistor, and the first vertical transistor is stacked on top of the second vertical transistor. The first vertical transistor is mounted on a lead frame with the source electrode of the first vertical transistor coupled to the lead frame. The second vertical transistor is stacked on the first vertical transistor with the source electrode of the second vertical transistor coupled to the drain electrode of the first vertical transistor.

Abstract translation: 本技术通常涉及半导体器件。 在一个实施例中，半导体器件包括第一垂直晶体管和第二垂直晶体管，并且第一垂直晶体管堆叠在第二垂直晶体管的顶部上。 第一垂直晶体管安装在引线框架上，第一垂直晶体管的源电极耦合到引线框架。 第二垂直晶体管堆叠在第一垂直晶体管上，其中第二垂直晶体管的源极耦合到第一垂直晶体管的漏极。

公开(公告)号：US08704292B2

公开(公告)日：2014-04-22

申请号：US12710968

申请日：2010-02-23

Applicant: Donald R. Disney

Inventor： Donald R. Disney

IPC: H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/47 ,  H01L29/4933 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/7828 ,  H01L29/7839

Abstract: Vertical capacitive depletion field effect transistors (VCDFETs) and methods for fabricating VCDFETs are disclosed. An example VCDFET includes one or more interleaved drift and gate regions. The gate region(s) may be configured to capacitively deplete the drift region(s) though one or more insulators that separate the gate region(s) from the drift region(s). The drift region(s) may have graded/non-uniform doping profiles. In addition, one or more ohmic and/or Schottky contacts may be configured to couple one or more source electrodes to the drift region(s).

Abstract translation: 公开了垂直电容耗尽场效应晶体管（VCDFET）和用于制造VCDFET的方法。 示例性VCDFET包括一个或多个交错漂移和栅极区域。 栅极区域可以被配置为通过将栅极区域与漂移区域分离的一个或多个绝缘体来电容耗尽漂移区域。 漂移区域可以具有渐变/非均匀掺杂分布。 另外，一个或多个欧姆和/或肖特基触点可以被配置成将一个或多个源极耦合到漂移区。

公开(公告)号：US20130299882A1

公开(公告)日：2013-11-14

申请号：US13468332

申请日：2012-05-10

Applicant: Donald R. Disney ,  Richard J. Brown ,  Hui Nie

Inventor： Donald R. Disney ,  Richard J. Brown ,  Hui Nie

IPC: H01L29/80 ,  H01L21/20

CPC classification number: H01L29/41741 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66446 ,  H01L29/8083

Abstract: A semiconductor device includes a III-nitride substrate and a channel structure coupled to the III-nitride substrate. The channel structure comprises a first III-nitride epitaxial material and is characterized by one or more channel sidewalls. The semiconductor device also includes a source region coupled to the channel structure. The source region comprises a second III-nitride epitaxial material. The semiconductor device further includes a III-nitride gate structure coupled to the one or more channel sidewalls, a gate metal structure in electrical contact with the III-nitride gate structure, and a dielectric layer overlying at least a portion of the gate metal structure. A top surface of the dielectric layer is substantially co-planar with a top surface of the source region.

Abstract translation: 半导体器件包括III族氮化物衬底和耦合到III族氮化物衬底的沟道结构。 沟道结构包括第一III族氮化物外延材料，其特征在于一个或多个沟道侧壁。 半导体器件还包括耦合到沟道结构的源极区域。 源区包括第二III族氮化物外延材料。 所述半导体器件还包括耦合到所述一个或多个沟道侧壁的III族氮化物栅极结构，与所述III族氮化物栅极结构电接触的栅极金属结构以及覆盖所述栅极金属结构的至少一部分的介电层。 电介质层的顶表面与源区的顶表面基本上共面。

公开(公告)号：US20130299873A1

公开(公告)日：2013-11-14

申请号：US13468325

申请日：2012-05-10

Applicant: Donald R. Disney ,  Richard J. Brown ,  Hui Nie

Inventor： Donald R. Disney ,  Richard J. Brown ,  Hui Nie

IPC: H01L29/80 ,  H01L21/335

CPC classification number: H01L29/8083 ,  H01L29/2003 ,  H01L29/66909

Abstract: A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region.

Abstract translation: 半导体器件包括III族氮化物衬底和耦合到III族氮化物衬底并且包括漂移区，沟道区和延伸区的第一III族氮化物外延层。 沟道区域通过漂移区域与III族氮化物衬底分离。 通道区域的特征在于第一宽度。 延伸区域通过沟道区域与漂移区域分离。 延伸区域的特征在于小于第一宽度的第二宽度。 半导体器件还包括耦合到延伸区域的顶表面的第二III族氮化物外延层，耦合到沟道区域的侧壁并相对于延伸区域横向自对准的III族氮化物栅极结构，以及 栅极金属结构与III族氮化物栅极结构电接触并且相对于延伸区域横向自对准。

公开(公告)号：US08525268B2

公开(公告)日：2013-09-03

申请号：US13022566

申请日：2011-02-07

Applicant: Donald R. Disney

Inventor： Donald R. Disney

IPC: H01L29/66

CPC classification number: H01L29/7802 ,  H01L24/06 ,  H01L24/48 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/781 ,  H01L29/8083 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The present technology discloses a vertical discrete device with gate and drain electrodes on the same surface and method for making the same. The vertical discrete device comprises a deep gate contact that couples the buried gate to a gate electrode which is formed on the same surface as the drain electrode. The discrete device according to the present technology can be used in co-packaging power management applications and the source electrode of the discrete device may be attached to the leadframe of the package.

Abstract translation: 本技术公开了一种在相同表面上具有栅电极和漏电极的垂直分立器件及其制造方法。 垂直分立器件包括将栅极连接到形成在与漏电极相同的表面上的栅电极的深栅极接触。 根据本技术的分立器件可以用于共包装电源管理应用中，并且分立器件的源电极可以附接到封装的引线框架。

公开(公告)号：US20130161780A1

公开(公告)日：2013-06-27

申请号：US13335329

申请日：2011-12-22

Applicant: Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Richard J. Brown ,  Donald R. Disney

Inventor： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Richard J. Brown ,  Donald R. Disney

IPC: H01L29/868 ,  H01L21/20

CPC classification number: H01L29/868 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/66204 ,  H01L29/66212 ,  H01L29/6631 ,  H01L29/66924

Abstract: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region

公开(公告)号：US20130161634A1

公开(公告)日：2013-06-27

申请号：US13335383

申请日：2011-12-22

Applicant: Donald R. Disney ,  Isik C. Kizilyalli ,  Linda Romano ,  Andrew Edwards ,  Hui Nie

Inventor： Donald R. Disney ,  Isik C. Kizilyalli ,  Linda Romano ,  Andrew Edwards ,  Hui Nie

IPC: H01L29/18 ,  H01L21/302

CPC classification number: H01L29/872 ,  H01L21/0495 ,  H01L21/2654 ,  H01L21/76224 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/402

Abstract: A method for fabricating an edge termination, which can be used in conjunction with GaN-based materials, includes providing a substrate of a first conductivity type. The substrate has a first surface and a second surface. The method also includes forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The substrate, the first GaN epitaxial layer and the second GaN epitaxial layer can be referred to as an epitaxial structure.

Abstract translation: 可以与GaN基材料一起使用的用于制造边缘终端的方法包括提供第一导电类型的衬底。 基板具有第一表面和第二表面。 该方法还包括形成耦合到衬底的第一表面的第一导电类型的第一GaN外延层，并形成与第一导电类型相反的第二导电类型的第二GaN外延层。 第二GaN外延层耦合到第一GaN外延层。 衬底，第一GaN外延层和第二GaN外延层可以被称为外延结构。

公开(公告)号：US20130161633A1

公开(公告)日：2013-06-27

申请号：US13334742

申请日：2011-12-22

Applicant: Hui Nie ,  Andrew P. Edwards ,  Donald R. Disney ,  Richard J. Brown ,  Isik C. Kizilyalli

Inventor： Hui Nie ,  Andrew P. Edwards ,  Donald R. Disney ,  Richard J. Brown ,  Isik C. Kizilyalli

IPC: H01L29/20 ,  H01L21/20

CPC classification number: H01L21/0254 ,  H01L21/2654 ,  H01L21/266 ,  H01L29/0611 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/66204 ,  H01L29/66212 ,  H01L29/66924 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

Abstract: A semiconductor structure includes a GaN substrate having a first surface and a second surface opposing the first surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a first GaN epitaxial layer of the first conductivity type coupled to the second surface of the GaN substrate and a second GaN epitaxial layer of a second conductivity type coupled to the first GaN epitaxial layer. The second GaN epitaxial layer includes an active device region, a first junction termination region characterized by an implantation region having a first implantation profile, and a second junction termination region characterized by an implantation region having a second implantation profile.

Abstract translation: 半导体结构包括具有第一表面和与第一表面相对的第二表面的GaN衬底。 GaN衬底的特征在于第一导电类型和第一掺杂剂浓度。 半导体结构还包括耦合到GaN衬底的第二表面的第一导电类型的第一GaN外延层和耦合到第一GaN外延层的第二导电类型的第二GaN外延层。 第二GaN外延层包括有源器件区，第一结端接区，其特征在于具有第一注入分布的注入区，以及第二结终端区，其特征在于具有第二注入分布的注入区。

公开(公告)号：US20130049076A1

公开(公告)日：2013-02-28

申请号：US13215116

申请日：2011-08-22

Applicant: Donald R. Disney

Inventor： Donald R. Disney

IPC: H01L27/06 ,  H01L21/8232

CPC classification number: H01L29/8725 ,  H01L27/0727 ,  H01L29/808 ,  H01L29/872

Abstract: The present invention discloses a power device with integrated power transistor and Schottky diode and a method for making the same. The power device comprises a power transistor having a drain region, a Schottky diode in the drain region of the power transistor, and a trench-barrier near the Schottky diode. The trench-barrier is provided to reduce a reverse leakage current of the Schottky diode and minimizes the possibility of introducing undesired parasitic bipolar junction transistor in the power device.

Abstract translation: 本发明公开了一种具有集成功率晶体管和肖特基二极管的功率器件及其制造方法。 功率器件包括功率晶体管，其功率晶体管具有漏极区，功率晶体管的漏极区中的肖特基二极管和肖特基二极管附近的沟槽势垒。 提供沟槽屏障以减少肖特基二极管的反向泄漏电流并且最小化在功率器件中引入不期望的寄生双极结型晶体管的可能性。

公开(公告)号：US20130020632A1

公开(公告)日：2013-01-24

申请号：US13185402

申请日：2011-07-18

Applicant: Donald R. Disney

Inventor： Donald R. Disney

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: A lateral transistor includes a gate formed over a gate oxide and a field plate formed over a thick gate oxide. The field plate is electrically connected to a source. The field plate is configured to capacitively deplete a drift region when the lateral transistor is in the OFF state.

Abstract translation: 横向晶体管包括形成在栅极氧化物上的栅极和形成在厚栅极氧化物上的场板。 场板电连接到源。 场板被配置为当横向晶体管处于截止状态时电容性地耗尽漂移区域。