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256 条记录 (耗时 0.026 秒)

    COMPUTING SYSTEM AND TRUSTED COMPUTING METHOD
    91.
    发明公开
    COMPUTING SYSTEM AND TRUSTED COMPUTING METHOD 审中-公开

    公开(公告)号：US20240143848A1

    公开(公告)日：2024-05-02

    申请号：US18189373

    申请日：2023-03-24

    申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

    发明人： Zhenhua HUANG ,  Yingbing GUAN ,  Yanting LI

    IPC分类号： G06F21/74 ,  G06F12/14 ,  G06F21/60

    CPC分类号： G06F21/74 ,  G06F12/1441 ,  G06F21/604

    摘要： A computing system with trusted computing is shown. The processor includes a normal core, and a trusted core for trusted computing. The system memory provides a normal memory, and an isolated memory for trusted computing. The chipset for the communication among the processor, the system memory, and peripherals includes a monitor and records memory protection configuration information. According to the memory protection configuration information, the monitor permits security peripherals to access the isolated memory, and prohibits normal peripherals from accessing the isolated memory.

    Memory device and operation method thereof
    93.
    发明授权
    Memory device and operation method thereof 有权

    公开(公告)号：US11842767B2

    公开(公告)日：2023-12-12

    申请号：US17082477

    申请日：2020-10-28

    申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

    发明人： Quansheng Li

    IPC分类号： G11C11/418 ,  G11C11/412 ,  G11C11/419

    CPC分类号： G11C11/418 ,  G11C11/412 ,  G11C11/419

    摘要： A memory device and an operation method for the memory device are provided. The memory device includes a memory block, a row decoder and a control circuit. The memory block includes a plurality of memory cells, wherein a row of memory cells in the memory block are coupled to at least one word line, and a column of memory cells in the memory block are coupled to a bit line and a multiplexer. The row decoder is coupled to the memory block and configured for the row of memory cells. The control circuit is coupled to the row decoder and indicates which word line, bit line and multiplexer is enabled.

    CACHE MEMORY DEVICE AND DATA CACHE METHOD
    97.
    发明公开
    CACHE MEMORY DEVICE AND DATA CACHE METHOD 审中-公开

    公开(公告)号：US20230169004A1

    公开(公告)日：2023-06-01

    申请号：US18048161

    申请日：2022-10-20

    申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

    发明人： Junjie ZHANG ,  Mengchen YANG ,  Jing QIAO ,  Jianbin WANG

    IPC分类号： G06F12/0846 ,  G06F12/0875

    CPC分类号： G06F12/0846 ,  G06F12/0875

    摘要： A cache memory device is provided in the disclosure. The cache memory device includes a first AGC, a compression circuit, a second AGC, a virtual tag array, and a comparator circuit. The first AGC generates a virtual address based on a load instruction. The compression circuit obtains the higher part of the virtual address and generates a target hash value based on the higher part of the virtual address. The second AGC generates the lower part of the virtual address based on the load instruction. The virtual tag array obtains the lower part and selects a set of memory units. The comparator circuit compares the target hash value to a hash value stored in each memory unit of the set of memory units. When the comparator circuit generates the virtual tag miss signal, the comparator circuit transmits the virtual tag miss signal to the reservation station.

    INTERCONNECT INTERFACE
    99.
    发明申请
    INTERCONNECT INTERFACE 有权

    公开(公告)号：US20230095940A1

    公开(公告)日：2023-03-30

    申请号：US17506124

    申请日：2021-10-20

    申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

    发明人： Weilin WANG ,  Fan YANG ,  Shuai ZHANG ,  Chunhui ZHENG ,  Peng SHEN

    IPC分类号： G06F13/40 ,  H04L29/08 ,  H04L1/00

    摘要： An interconnect interface is applied between sockets or between dies. The interconnect interface includes a first transmitter (TX), a first receiver (RX), and an electrical physical layer (EPHY) coupled between the first TX and the first RX. The data provided by a first device is transmitted from the first TX to the EPHY and then received by the first RX to be retrieved by a second device. The first TX includes an arbiter for arbitrating between a plurality of channels of the first device to obtain data from the first device. The first TX includes a packet generator, which packs the data obtained from the first device into a packet to be transmitted through the EPHY. The first TX further includes a first buffer that backs up the data obtained from the first device for retransmission.

    Output stage circuit
    100.
    发明授权
    Output stage circuit 有权

    公开(公告)号：US11451197B2

    公开(公告)日：2022-09-20

    申请号：US16987337

    申请日：2020-08-06

    申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

    发明人： Shen Li ,  Zhongding Liu

    IPC分类号： H03F3/16 ,  H03K5/24

    摘要： An output stage circuit comprising a bias voltage generator, a first amplifier circuit and a second amplifier circuit is provided. The bias voltage generator is coupled to an output terminal of the output stage circuit to generate a bias voltage according to an output voltage of the output terminal. The first amplifier circuit is coupled to the output terminal, a first power supply terminal and the bias voltage generator, receives a first pre-driving signal, a first predetermined voltage and the bias voltage, and determines whether to transmit a first voltage to serve as the output voltage. The second amplifier circuit is coupled to the output terminal, a second power supply terminal and the bias voltage generator, receives a second pre-driving signal, a second predetermined voltage and the bias voltage, and determines whether to transmit a second voltage to serve as the output voltage.