公开(公告)号：US20230083411A1

公开(公告)日：2023-03-16

申请号：US17837559

申请日：2022-06-10

申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

发明人： Yanting LI ,  Zhenhua HUANG ,  Yingbing GUAN ,  Yun SHEN ,  Lei YI ,  Shuang YANG

IPC分类号： H04L9/30 ,  G06F9/30

摘要： A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has a first register, storing a public key pointer pointing to a public key. In response to a single elliptic curve cryptographic instruction of an instruction set architecture, the processor reads a plaintext input from a first storage space within a system memory, performing an encryption procedure using the elliptic curve cryptographic algorithm on the plaintext input based on the public key obtained by referring to the first register to encrypt the plaintext input and to generate a ciphertext output, and programming the ciphertext output into a second storage space within the system memory.

公开(公告)号：US20230066718A1

公开(公告)日：2023-03-02

申请号：US17837695

申请日：2022-06-10

申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

发明人： Zhenhua HUANG ,  Yingbing GUAN ,  Yanting LI

IPC分类号： H04L9/06

摘要： A processor with a Hash cryptographic algorithm and a data processing method are shown. In response to one single Hash cryptographic instruction of an instruction set architecture, the processor reads a first storage space within a system memory to obtain an input message of a limited length, and processes the input message in accordance with the Hash cryptographic algorithm to generate a final Hash value of a specific length.

公开(公告)号：US20230078830A1

公开(公告)日：2023-03-16

申请号：US17837582

申请日：2022-06-10

申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

发明人： Yanting LI ,  Zhenhua HUANG ,  Yingbing GUAN ,  Yun SHEN ,  Lei YI ,  Shuang YANG

IPC分类号： H04L9/30 ,  G06F9/22 ,  G06F9/30

摘要： A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has a first register, storing a private key pointer pointing to a private key. In response to a single elliptic curve cryptographic instruction of an instruction set architecture, the processor reads a ciphertext input from a first storage space within a system memory, performing a decryption procedure using the elliptic curve cryptographic algorithm on the ciphertext input based on the private key obtained by referring to the first register to decrypt the ciphertext input and generate a plaintext output, and programming the plaintext output into a second storage space within the system memory.

公开(公告)号：US20190227795A1

公开(公告)日：2019-07-25

申请号：US16163818

申请日：2018-10-18

申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

发明人： Jing CHEN ,  Xiaoyang LI ,  Juanli SONG ,  Zhenhua HUANG ,  Weilin WANG ,  Jiin LAI

IPC分类号： G06F9/22 ,  G06F9/448 ,  G06F9/30

摘要： A microprocessor for neural network computing having a mapping table, a microcode memory, and a microcode decoding finite-state machine (FSM) is disclosed. According to the mapping table, a macroinstruction is mapped to an address on the microcode memory. The microcode decoding FSM decodes contents which are retrieved from the microcode memory according to the address, to get microinstructions involving at least one microinstruction loop that is repeated to operate a datapath to complete the macroinstruction.

公开(公告)号：US20240179001A1

公开(公告)日：2024-05-30

申请号：US18461780

申请日：2023-09-06

申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

发明人： Zhenhua HUANG ,  Yingbing GUAN ,  Yanting LI ,  Gangru XUE ,  Mingxiu LI

IPC分类号： H04L9/32

CPC分类号： H04L9/32

摘要： A processor for building a homogeneous dual computing system is shown. The processor provides two homogeneous cores. One is used as a trusted core and the other is used as a master core. The trusted core has an access right to an isolated storage space of a system memory. The master core is a normal core that is prohibited from accessing the isolated storage space. The trusted core has a first cryptographic module. In response to a reset of the trusted core, the first cryptographic module operates for firmware verification. This is how the trusted core turns on the processor using trusted firmware.

公开(公告)号：US20240143848A1

公开(公告)日：2024-05-02

申请号：US18189373

申请日：2023-03-24

申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

发明人： Zhenhua HUANG ,  Yingbing GUAN ,  Yanting LI

IPC分类号： G06F21/74 ,  G06F12/14 ,  G06F21/60

CPC分类号： G06F21/74 ,  G06F12/1441 ,  G06F21/604

摘要： A computing system with trusted computing is shown. The processor includes a normal core, and a trusted core for trusted computing. The system memory provides a normal memory, and an isolated memory for trusted computing. The chipset for the communication among the processor, the system memory, and peripherals includes a monitor and records memory protection configuration information. According to the memory protection configuration information, the monitor permits security peripherals to access the isolated memory, and prohibits normal peripherals from accessing the isolated memory.

公开(公告)号：US20220137661A1

公开(公告)日：2022-05-05

申请号：US17509374

申请日：2021-10-25

申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

发明人： Jiamin SITU ,  Zhenhua HUANG ,  Yang SHI ,  Jun WU

IPC分类号： G06F1/12

摘要： An electronic device comprises a first processor, a second processor and a communication interface. The first processor operates according to a first clock, and comprises a first time-stamp counter to count the first clock to obtain a first count value. The second processor operates according to a second clock, and comprises a second time-stamp counter to count the second clock to obtain a second count value. The communication interface is coupled between the first processor and the second processor. The first processor periodically sends the first count value to the second processor through the communication interface. When the second processor receives the first count value, the second processor adds a preset deviation value to the first count value to obtain a synchronization value, resets the second count value, and the sum of the synchronization value and the second count value is read by the second processor.

公开(公告)号：US20240143851A1

公开(公告)日：2024-05-02

申请号：US18189381

申请日：2023-03-24

申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

发明人： Zhenhua HUANG ,  Yingbing GUAN ,  Yanting LI

IPC分类号： G06F21/85 ,  G06F13/24

CPC分类号： G06F21/85 ,  G06F13/24

摘要： A trusted computing technology is shown. An isolated memory stores a security interrupt descriptor table (SIDT) to correspond to security interrupts triggered by security peripherals. A first register of the trusted core stores a first address pointing to the SIDT. A local advanced programmable interrupt controller in the trusted core provides an interrupt arbiter that arbitrates between peripheral interrupts received from the chipset. When producing an arbitration result showing that a target interrupt is a security interrupt, the interrupt arbiter outputs a security interrupt request and a security interrupt vector to trigger the trusted core to search the SIDT indicated by the first register, to get a target security interrupt descriptor for execution of the corresponding interrupt program.

公开(公告)号：US20230085569A1

公开(公告)日：2023-03-16

申请号：US17837607

申请日：2022-06-10

申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

发明人： Yanting LI ,  Zhenhua HUANG ,  Yingbing GUAN ,  Yun SHEN ,  Lei YI ,  Shuang YANG

IPC分类号： H04L9/32 ,  G06F9/30

摘要： A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has first register storing a Hash value pointer, and a second register, storing a private key pointer. In response to a first elliptic curve cryptographic instruction of an instruction set architecture, the processor reads a first storage space within a system memory by referring to the first register to get a Hash value of the data to be signed, reads a private key by referring to the second register, performs a signature procedure using the elliptic curve cryptographic algorithm on the Hash value based on the private key to generate a digital signature, and programs the digital signature into a second storage space within the system memory.

公开(公告)号：US20190227770A1

公开(公告)日：2019-07-25

申请号：US16163790

申请日：2018-10-18

申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

发明人： Jing CHEN ,  Xiaoyang LI ,  Juanli SONG ,  Zhenhua HUANG ,  Weilin WANG ,  Jiin LAI

IPC分类号： G06F7/533 ,  G06F9/22 ,  G06F7/499 ,  G06F9/30 ,  G06F15/78

摘要： A microprocessor provides at least two storage areas and uses a datapath for Booth multiplication. According to a first and second field of a microinstruction, the datapath gets multiplicand number supply data from the first storage area and multiplier number supply data from the second storage area. The datapath operates according to a word length indicated in a third field of the microinstruction. The datapath gets multi-bit acquisitions for Booth multiplication from the multiplier number supply data. The datapath divides the multiplicand number supply data into multiplicand numbers according to the word length, and performs Booth multiplication on the multiplicand numbers based on the multi-bit acquisitions to get partial products. According to the word length, the datapath selects a part of the partial products to be shifted and added for generation of a plurality of products.